Ryuichi Fujimoto

According to our database1, Ryuichi Fujimoto authored at least 42 papers between 1996 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


On csauthors.net:


A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems.
IEEE J. Solid State Circuits, 2022

A Noise-Canceling Charge Pump for Area Efficient PLL Design.
IEICE Trans. Electron., 2021

Adaptive Quantization Method for CNN with Computational-Complexity-Aware Regularization.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Quantization Strategy for Pareto-optimally Low-cost and Accurate CNN.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

Weight Compression MAC Accelerator for Effective Inference of Deep Learning.
IEICE Trans. Electron., 2020

A 12.8-Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems.
IEEE J. Solid State Circuits, 2019

Performance Evaluation of Age Estimation from T1-Weighted Images Using Brain Local Features and CNN.
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018

An 18 µW Spur Cancelled Clock Generator for Recovering Receiver Sensitivity in Wireless SoCs.
IEICE Trans. Electron., 2017

Age estimation from brain MRI images using deep learning.
Proceedings of the 14th IEEE International Symposium on Biomedical Imaging, 2017

A low voltage 0.8V RF receiver in 28nm CMOS for 5GHz WLAN.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

Brain age estimation from T1-weighted images using effective local features.
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017

Analog and Digital Collaborative Design Techniques for Wireless SoCs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

An 18 µW spur canceled clock generator for recovering receiver sensitivity in wireless SoCs.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

Age estimation using effective brain local features from T1-weighted images.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016

All-digital single-inductor multiple-output DC-DC converter with over 65.3% efficiency in 1 uW to 50 mW load range and 86.3% peak efficiency.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

3D-integrated, low-height, small module design techniques for 4.48GHz, 560MHz-bandwidth TransferJet™ transceiver.
Proceedings of the 2014 IEEE Radio and Wireless Symposium, 2014

A 0.171-mW, 2.4-GHz Class-D VCO with dynamic supply voltage control.
Proceedings of the ESSCIRC 2014, 2014

98 mW 10 Gbps Wireless Transceiver Chipset With D-Band CMOS Circuits.
IEEE J. Solid State Circuits, 2013

A -70 dBm-Sensitivity 522 Mbps 0.19 nJ/bit-TX 0.43 nJ/bit-RX Transceiver for TransferJet<sup>TM</sup> SoC in 65 nm CMOS.
IEICE Trans. Electron., 2013

A 120 GHz/140 GHz Dual-Channel OOK Receiver Using 65 nm CMOS Technology.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

IEICE Trans. Electron., 2013

14.4mW 10Gbps CMOS limiting amplifier with local DC offset cancellers.
Proceedings of the 2013 IEEE Radio and Wireless Symposium, 2013

A-104 dBc/Hz In-Band Phase Noise 3 GHz All Digital PLL with Phase Interpolation Based Hierarchical Time to Digital Converter.
IEICE Trans. Electron., 2012

Bias-Voltage-Dependent Subcircuit Model for Millimeter-Wave CMOS Circuit.
IEICE Trans. Electron., 2012

A 120-GHz Transmitter and Receiver Chipset with 9-Gbps Data Rate Using 65-nm CMOS Technology.
IEICE Trans. Electron., 2012

135 GHz 98 mW 10 Gbps ASK transmitter and receiver chipset in 40 nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012

A -70dBm-sensitivity 522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX transceiver for TransferJet™ SoC in 65nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012

Analysis of De-Embedding Error Cancellation in Cascade Circuit Design.
IEICE Trans. Electron., 2011

A Single-Chip RF Tuner/OFDM Demodulator for Mobile Digital TV Application.
IEICE Trans. Electron., 2011

Device Modeling Techniques for High-Frequency Circuits Design Using Bond-Based Design at over 100 GHz.
IEICE Trans. Electron., 2011

140GHz CMOS amplifier with group delay variation of 10.2ps and 0.1dB bandwidth of 12GHz.
IEICE Electron. Express, 2011

A 60-GHz Phase-Locked Loop with Inductor-Less Wide Operation Range Prescaler in 90-nm CMOS.
IEICE Trans. Electron., 2009

A 60-GHz CMOS Receiver Front-End With Frequency Synthesizer.
IEEE J. Solid State Circuits, 2008

A Low-Noise Amplifier for WCDMA Terminal with High Tolerance for Leakage Signal from Transmitter.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

A Quadrature Demodulator for WCDMA Receiver Using Common-Base Input Stage with Robustness to Transmitter Leakage.
IEICE Trans. Electron., 2007

A 60-GHz phase-locked loop with inductor-less prescaler in 90-nm CMOS.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

A Direct Conversion Receiver for W-CDMA Reducing Current Consumption to 31 mA.
IEICE Trans. Electron., 2005

A Low LO Leakage and Low Power LO Buffer for Direct-Conversion Quadrature Demodulator.
IEICE Trans. Electron., 2005

A 7-GHz 1.8-dB NF CMOS low-noise amplifier.
IEEE J. Solid State Circuits, 2002

A 2.7-V, 200-kHz, 49-dBm, stopband-IIP3, low-noise, fully balanced gm-C filter IC.
IEEE J. Solid State Circuits, 1999

A low local input 1.9 GHz Si-bipolar quadrature modulator with no adjustment.
IEEE J. Solid State Circuits, 1996