Daisuke Miyashita

Orcid: 0000-0003-2108-3397

According to our database1, Daisuke Miyashita authored at least 32 papers between 2005 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
SimplyRetrieve: A Private and Lightweight Retrieval-Centric Generative AI Tool.
CoRR, 2023

Can a Frozen Pretrained Language Model be used for Zero-shot Neural Retrieval on Entity-centric Questions?
CoRR, 2023

RaLLe: A Framework for Developing and Evaluating Retrieval-Augmented Large Language Models.
Proceedings of the 2023 Conference on Empirical Methods in Natural Language Processing, 2023

2022
Revisiting a kNN-Based Image Classification System with High-Capacity Storage.
Proceedings of the Computer Vision - ECCV 2022, 2022

2021
Adaptive Quantization Method for CNN with Computational-Complexity-Aware Regularization.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Quantization Strategy for Pareto-optimally Low-cost and Accurate CNN.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2020
Weight Compression MAC Accelerator for Effective Inference of Deep Learning.
IEICE Trans. Electron., 2020

2019
A 12.8-Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems.
IEEE J. Solid State Circuits, 2019

Live Demonstration: FPGA-Based CNN Accelerator with Filter-Wise-Optimized Bit Precision.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Post Training Weight Compression with Distribution-based Filter-wise Quantization Step.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2019

2018
A 12.8 GB/S Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth and Large-Capacity Storage Systems.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

FPGA-based CNN Processor with Filter-Wise-Optimized Bit Precision.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
A Neuromorphic Chip Optimized for Deep Learning and CMOS Technology With Time-Domain Analog and Digital Mixed-Signal Processing.
IEEE J. Solid State Circuits, 2017

LogNet: Energy-efficient neural networks using logarithmic computation.
Proceedings of the 2017 IEEE International Conference on Acoustics, 2017

2016
Convolutional Neural Networks using Logarithmic Data Representation.
CoRR, 2016

Time-domain neural network: A 48.5 TSOp/s/W neuromorphic chip optimized for deep learning and CMOS technology.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
Mixed-signal circuits for embedded machine-learning applications.
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015

2014
An LDPC Decoder With Time-Domain Analog and Digital Mixed-Signal Processing.
IEEE J. Solid State Circuits, 2014

3D-integrated, low-height, small module design techniques for 4.48GHz, 560MHz-bandwidth TransferJet™ transceiver.
Proceedings of the 2014 IEEE Radio and Wireless Symposium, 2014

19.3 66.3KIOPS-random-read 690MB/s-sequential-read universal Flash storage device controller with unified memory extension.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
A -70 dBm-Sensitivity 522 Mbps 0.19 nJ/bit-TX 0.43 nJ/bit-RX Transceiver for TransferJet<sup>TM</sup> SoC in 65 nm CMOS.
IEICE Trans. Electron., 2013

A 10.4pJ/b (32, 8) LDPC decoder with time-domain analog and digital mixed-signal processing.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A supply-noise-rejection technique in ADPLL with noise-cancelling current source.
Proceedings of the ESSCIRC 2013, 2013

2012
A-104 dBc/Hz In-Band Phase Noise 3 GHz All Digital PLL with Phase Interpolation Based Hierarchical Time to Digital Converter.
IEICE Trans. Electron., 2012

A -70dBm-sensitivity 522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX transceiver for TransferJet™ SoC in 65nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012

2011
A Low-Noise and Highly-Linear Transmitter with Envelope Injection Pre-Power Amplifier for Multi-Mode Radio.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

2010
A Fully Integrated 2 ˟ 1 Dual-Band Direct-Conversion Mobile WiMAX Transceiver With Dual-Mode Fractional Divider and Noise-Shaping Transimpedance Amplifier in 65 nm CMOS.
IEEE J. Solid State Circuits, 2010

A fully integrated 2×1 dual-band direct-conversion transceiver with dual-mode fractional divider and noise-shaping TIA for mobile WiMAX SoC in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
A 0.6V 380µW -14dBm LO-input 2.4GHz double-balanced current-reusing single-gate CMOS mixer with cyclic passive combiner.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
A 1.2V 0.2-to-6.3GHz Transceiver with Less Than -29.5dB EVM@-3dBm and a Choke/Coil-Less Pre-Power Amplifier.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2006
Monolithically Integrated Mach-Zehnder Interferometer All-Optical Switches by Selective Area MOVPE.
IEICE Trans. Electron., 2006

2005
A phase noise minimization of CMOS VCOs over wide tuning range and large PVT variations.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005


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