Huy Cu Ngo

Orcid: 0000-0002-3678-7058

According to our database1, Huy Cu Ngo authored at least 6 papers between 2017 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

On csauthors.net:

Bibliography

2022
A 56-Gb/s PAM4 Transceiver with False-Lock-Aware Locking Scheme for Mueller-Müller CDR.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

2021
A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2018
A Sub-mW Fractional-N ADPLL With FOM of -246 dB for IoT Applications.
IEEE J. Solid State Circuits, 2018

A 0.98mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of -246dB for IoT applications in 65nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017
8.5 A 0.42ps-jitter -241.7dB-FOM synthesizable injection-locked PLL with noise-isolation LDO.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017


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