Zewen Cao
Orcid: 0009-0003-2951-2130
According to our database1,
Zewen Cao authored at least 6 papers
between 2012 and 2026.
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
2026
I-COR: Instruction-Level Fault Tolerance for Register File in 3-Stage Pipeline RISC-V Processors.
ACM Trans. Embed. Comput. Syst., March, 2026
MergFS: Efficient Bridging of a 32-bit High-Speed Intra-Core Bus to a 64-bit Low-Speed AHB-Lite Bus.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2026
2025
RIVL: A Low-Cost SoC Agile Development Platform for Multiple RISC-V Processors Design and Verification.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2025
2017
Proceedings of the International Conference on Big Data and Internet of Things, 2017
2015
Proceedings of the 2015 International Conference on Behavioral, 2015
2012
Proceedings of the 2012 Second International Conference on Cloud and Green Computing, 2012