Hualong Zhao

Orcid: 0009-0009-9502-5510

According to our database1, Hualong Zhao authored at least 8 papers between 2008 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
MergFS: Efficient Bridging of a 32-bit High-Speed Intra-Core Bus to a 64-bit Low-Speed AHB-Lite Bus.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2026

2025
RIVL: A Low-Cost SoC Agile Development Platform for Multiple RISC-V Processors Design and Verification.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2025

2023
Residual Dense Blocks and Contrastive Regularization Integrated Underwater Image Enhancement Network.
IEEE Access, 2023

2018
Design and Hardware Implementation of a STT-MRAM Based SoC Architecture for Smart Card Chip.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2009
Research and Application of PBL Mode in GIS Course Teaching.
Proceedings of the International Forum on Information Technology and Applications, 2009

Study on Group Decision Making Based on Different Preference Information.
Proceedings of the First International Workshop on Database Technology and Applications, 2009

2008
The Design and Implementation of a High Performance and High Flexibility Memory Interface Architecture for Embedded Application.
Proceedings of the 9th International Conference for Young Computer Scientists, 2008

GEMI: A High Performance and High Flexibility Memory Interface Architecture for Complex Embedded SOC.
Proceedings of the International Conference on Computer Science and Software Engineering, 2008


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