Zhangxiaowen Gong

According to our database1, Zhangxiaowen Gong authored at least 8 papers between 2017 and 2026.

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Bibliography

2026
AccelFlow: Orchestrating an On-Package Ensemble of Fine-Grained Accelerators for Microservices.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2026

2022
Graphite: optimizing graph neural networks on CPUs through cooperative software-hardware techniques.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

2020
SAVE: Sparsity-Aware Vector Engine for Accelerating DNN Training and Inference on CPUs.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

SparseTrain: Leveraging Dynamic Sparsity in Software for Training DNNs on General-Purpose SIMD Processors.
Proceedings of the PACT '20: International Conference on Parallel Architectures and Compilation Techniques, 2020

2019
SparseTrain: Leveraging Dynamic Sparsity in Training DNNs on General-Purpose SIMD Processors.
CoRR, 2019

2018
An empirical study of the effect of source-level loop transformations on compiler stability.
Proc. ACM Program. Lang., 2018

2017
Using Hardware Counters to Predict Vectorization.
Proceedings of the Languages and Compilers for Parallel Computing, 2017

LORE: A loop repository for the evaluation of compilers.
Proceedings of the 2017 IEEE International Symposium on Workload Characterization, 2017


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