Zhao Zhang

Affiliations:
  • Iowa State University, Department of Electrical and Computer Engineering, Ames, IA, USA
  • College of William and Mary, Department of Computer Science, Williamsburg, VA, USA (PhD 2002)


According to our database1, Zhao Zhang authored at least 48 papers between 1998 and 2021.

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Bibliography

2021
Discreet-PARA: Rowhammer Defense with Low Cost and High Efficiency.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021

2015
Flexible memory: A novel main memory architecture with block-level memory compression.
Proceedings of the 10th IEEE International Conference on Networking, 2015

Memory design for selective error protection.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

2014
MASTER: A Multicore Cache Energy-Saving Technique Using Dynamic Cache Reconfiguration.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Automatic runtime frequency-scaling system for energy savings in parallel applications.
J. Supercomput., 2014

Secure, Efficient and Fine-Grained Data Access Control Mechanism for P2P Storage Cloud.
IEEE Trans. Cloud Comput., 2014

Mini-Rank: A Power-EfficientDDRx DRAM Memory Architecture.
IEEE Trans. Computers, 2014

A Host-Based Approach for Unknown Fast-Spreading Worm Detection and Containment.
ACM Trans. Auton. Adapt. Syst., 2014

Encache: a Dynamic Profiling-Based Reconfiguration Technique for Improving Cache Energy Efficiency.
J. Circuits Syst. Comput., 2014

MemGuard: A low cost and energy efficient design to support and enhance memory system reliability.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

2013
Thermal Modeling and Management of DRAM Systems.
IEEE Trans. Computers, 2013

E<sup>3</sup>CC: A memory error protection scheme with novel address mapping for subranked and low-power memories.
ACM Trans. Archit. Code Optim., 2013

Energy saving strategies for parallel applications with point-to-point communication phases.
J. Parallel Distributed Comput., 2013

Achieving energy efficiency during collective communications.
Concurr. Comput. Pract. Exp., 2013

FlexiWay: A cache energy saving technique using fine-grained cache reconfiguration.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Free ECC: An efficient error protection for compressed last-level caches.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

2011
Memory Architecture for Integrating Emerging Memory Technologies.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010
An Application-Level Data Transparent Authentication Scheme without Communication Overhead.
IEEE Trans. Computers, 2010

Enhancing adaptive middleware for quantum chemistry applications with a database framework.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Exploring Tuning Strategies for Quantum Chemistry Computations.
Proceedings of the Software Automatic Tuning, From Concepts to State-of-the-Art Results, 2010

2009
Enabling software management for multicore caches with a lightweight hardware support.
Proceedings of the ACM/IEEE Conference on High Performance Computing, 2009

Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

Electronic Structure Calculations and Adaptation Scheme in Multi-core Computing Environments.
Proceedings of the Computational Science, 2009

Soft-OLP: Improving Hardware Cache Performance through Software-Controlled Object-Level Partitioning.
Proceedings of the PACT 2009, 2009

2008
Reflections on Teaching and Learning in an Advanced Undergraduate Course in Embedded Systems.
IEEE Trans. Educ., 2008

Software thermal management of dram memory for multicore systems.
Proceedings of the 2008 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, 2008

Mini-rank: Adaptive DRAM architecture for improving memory power efficiency.
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

BotTracer: Execution-Based Bot-Like Malware Detection.
Proceedings of the Information Security, 11th International Conference, 2008

Memory Access Scheduling Schemes for Systems with Multi-Core Processors.
Proceedings of the 2008 International Conference on Parallel Processing, 2008

Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems.
Proceedings of the 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 2008

2007
DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving.
Proceedings of the 2007 IEEE International Symposium on Performance Analysis of Systems and Software, 2007

Thermal modeling and management of DRAM memory systems.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

2006
Component-oriented version management for hardware software co-design.
Proceedings of the 2006 conference of the Centre for Advanced Studies on Collaborative Research, 2006

2005
Performance Modeling and Tuning Strategies of Mixed Mode Collective Communications.
Proceedings of the ACM/IEEE SC2005 Conference on High Performance Networking and Computing, 2005

Towards Pairing Java Applications on SMT Processors.
Proceedings of the 13th International Symposium on Modeling, 2005

Performance Characterization of Java Applications on SMT Processors.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005

A Performance Comparison of DRAM Memory System Optimizations for SMT Processors.
Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005

2004
Design and Optimization of Large Size and Low Overhead Off-Chip Caches.
IEEE Trans. Computers, 2004

Heuristic-Based Scheduling to Maximize Throughput of Data-Intensive Grid Applications.
Proceedings of the Distributed Computing, 2004

An Efficient Anonymity Protocol for Grid Computing.
Proceedings of the 5th International Workshop on Grid Computing (GRID 2004), 2004

2002
Fine-Grain Priority Scheduling on Multi-Channel Memory Systems.
Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002

2001
Fast Bit-Reversals on Uniprocessors and Shared-Memory Multiprocessors.
SIAM J. Sci. Comput., 2001

Cached DRAM for ILP Processor Memory Access Latency Reduction.
IEEE Micro, 2001

Breaking Address Mapping Symmetry at Multi-levels of Memory Heirarchy to Reduce DRAM Row-buffer Conflicts.
J. Instr. Level Parallelism, 2001

2000
Cacheminer: A Runtime Approach to Exploit Cache Locality on SMP.
IEEE Trans. Parallel Distributed Syst., 2000

A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality.
Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000

1999
Cache-Optimal Methods for Bit-Reversals.
Proceedings of the ACM/IEEE Conference on Supercomputing, 1999

1998
A memory-layout oriented run-time technique for locality optimization.
Proceedings of the 1998 International Conference on Parallel Processing (ICPP '98), 1998


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