Zhi Jin

Orcid: 0000-0002-7630-0021

According to our database¹, Zhi Jin authored at least 4 papers between 2014 and 2025.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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Bibliography

2025

A 112-Gb/s PAM-4 Retimer Transceiver With Jitter-Filtering Clocking Scheme and BER Optimization Technique in 28-nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, July, 2025

A 100 Gb/s PAM4 receiver analog front-end with 33.1-dB boost in 28-nm CMOS process.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2025

2022

A 35-GHz Bandwidth 30 GSa/s InP Track-and-Hold Amplifier Using Enhanced f<sub>T</sub>-Doubler Technique.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

2014

A 4-GS/s 8-bit two-channel time-interleaved folding and interpolating ADC.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2014

Zhi Jin

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