Abhishek Patyal

According to our database, Abhishek Patyal authored at least 9 papers between 2018 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

On Reducing LDE Variations in Modern Analog Placement.

A. K. Thasreefa, Abhishek Patyal, Hao-Yu Chi, Mark Po-Hung Lin, Hung-Ming Chen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023

Pole-Aware Analog Layout Synthesis Considering Monotonic Current Flows and Wire Crossings.

Abhishek Patyal, Hung-Ming Chen, Mark Po-Hung Lin, Guan-Qi Fang, Simon Yi-Hung Chen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

2021

Improving the Quality of FPGA RO-PUF by Principal Component Analysis (PCA).

K. A. Asha, Li En Hsu, Abhishek Patyal, Hung-Ming Chen

ACM J. Emerg. Technol. Comput. Syst., 2021

2020

Exploring Multiple Analog Placements With Partial-Monotonic Current Paths and Symmetry Constraints Using PCP-SP.

Abhishek Patyal, Po-Cheng Pan, K. A. Asha, Hung-Ming Chen, Wei-Zen Chen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Achieving Analog Layout Integrity through Learning and Migration Invited Talk.

Mark Po-Hung Lin, Hao-Yu Chi, Abhishek Patyal, Zheng-Yao Liu, Jun-Jie Zhao, Chien-Nan Jimmy Liu, Hung-Ming Chen

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Late Breaking Results: Pole-aware Analog Placement Considering Monotonic Current Flow and Crossing-Wire Minimization.

Abhishek Patyal, Hung-Ming Chen, Mark Po-Hung Lin

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2018

On Closing the Gap Between Pre-Simulation and Post-Simulation Results in Nanometer Analog Layouts.

Po-Cheng Pan, Hung-Wen Huang, Chien-Chia Huang, Abhishek Patyal, Hung-Ming Chen, Tsun-Yu Yang

Proceedings of the 15th International Conference on Synthesis, 2018

Analog placement with current flow and symmetry constraints using PCP-SP.

Abhishek Patyal, Po-Cheng Pan, K. A. Asha, Hung-Ming Chen, Hao-Yu Chi, Chien-Nan Liu

Proceedings of the 55th Annual Design Automation Conference, 2018

Generation of PUF-Keys on FPGAs by K-means Frequency Clustering.

K. A. Asha, Abhishek Patyal, Hung-Ming Chen

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2018