Wei-Zen Chen

Orcid: 0000-0003-2840-0754

According to our database1, Wei-Zen Chen authored at least 62 papers between 1998 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
A 10 GHz Dual-Loop PLL With Active Cycle-Jitter Correction Achieving 12dB Spur and 29% Jitter Reduction.
IEEE Open J. Circuits Syst., 2024

2023
A 103 fJ/b/dB, 10-26 Gb/s Receiver With a Dual Feedback Nested Loop CDR for Wide Bandwidth Jitter Tolerance Enhancement.
IEEE J. Solid State Circuits, October, 2023

A Reference-Free Phase Noise Measurement Circuit Achieving 24.2-fs Periodic Jitter Sensitivity and 275-fsrms Resolution With Background Self-Calibration.
IEEE J. Solid State Circuits, 2023

2021
A 50 Gb/s PAM-4 Transmitter With Feedforward Equalizer and Background Phase Error Calibration.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

A 32 Gb/s PAM-4 Optical Transceiver With Active Back Termination in 40 nm CMOS Technology.
IEEE Open J. Circuits Syst., 2021

Introduction to the Special Section on the 2020 Asian Solid-State Circuits Conference (A-SSCC).
IEEE J. Solid State Circuits, 2021

Session 11 Overview: Advanced Wireline Links and Techniques Wireline Subcommittee.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

F6: Optical and Electrical Transceivers for 400GbE and Beyond.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

A 10 GHz Dual-Loop PLL with Active Noise Cancellation Achieving 12dB Spur and 29% Noise Reduction.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

A Single-Channel 1.75GS/s, 6-Bit Flash-Assisted SAR ADC with Self-Adaptive Timer and On-Chip Offset Calibration.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

A 1.68-23.2 Gb/s Reference-Less Half-Rate Receiver with an ISI-Tolerant Unlimited Range Frequency Detector.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020
Exploring Multiple Analog Placements With Partial-Monotonic Current Paths and Symmetry Constraints Using PCP-SP.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Millimeter-Wave Frequency Synthesizer for 60 GHz Wireless Interconnect.
Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020

A 50 Gb/s PAM-4 Transmitter with Feedforward Equalizer and Background Phase Error Calibration.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020

2019
A 25-Gb/s, 2.1-pJ/bit, Fully Integrated Optical Receiver With a Baud-Rate Clock and Data Recovery.
IEEE J. Solid State Circuits, 2019

2018
A 20-Gb/s, 2.4 pJ/bit, Fully Integrated Optical Receiver with a Baud-Rate Clock and Data Recovery.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A 40 Gb/s PAM-4 Receiver with 2-Tap DFE Based on Automatically Non-Even Level Tracking.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
A 25 Gb/s 1.13 pJ/b -10.8 dBm Input Sensitivity Optical Receiver in 40 nm CMOS.
IEEE J. Solid State Circuits, 2017

2016
Distortion-characteristic estimation predistorter for high efficiency power amplifiers.
IET Signal Process., 2016

A ΔΣ TDC with sub-ps resolution for PLL built-in phase noise measurement.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

2015
A Low-Jitter Cell-Based Digitally Controlled Oscillator With Differential Multiphase Outputs.
IEEE Trans. Very Large Scale Integr. Syst., 2015

A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter Suppression.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A 3.12 pJ/bit, 19-27 Gbps Receiver With 2-Tap DFE Embedded Clock and Data Recovery.
IEEE J. Solid State Circuits, 2015

A 25-Gb/s, -10.8-dBm input sensitivity, PD-bandwidth tolerant CMOS optical receiver.
Proceedings of the Symposium on VLSI Circuits, 2015

A 0.4V 53dB SNDR 250 MS/s time-based CT ΔΣ analog to digital converter.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
A 160-GHz Frequency-Translation Phase-Locked Loop With RSSI Assisted Frequency Acquisition.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

An automatic synthesis tool for nanometer low dropout regulator using simulation based model and geometric programming.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

A 0.6 V, 1.66mW energy harvester and audio driver for tympanic membrane transducer with wirelessly optical signal and power transfer.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A 2 × 20-Gb/s, 1.2-pJ/bit, time-interleaved optical receiver in 40-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

A 3.12 pJ/bit, 19-27 Gbps receiver with 2 Tap-DFE embedded clock and data recovery.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

An 8 Gbps, 4: 1 transition-aware self-toggling multiplexer.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
Wide Tunning Range 60 GHz VCO and 40 GHz DCO Using Single Variable Inductor.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A 10Bit, 10MS/s, low power cyclic ADC.
Proceedings of 2013 International Conference on IC Design & Technology, 2013

A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppression.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

A 0.1-3GHz cell-based fractional-N all digital phase-locked loop using ΔΣ noise-shaped phase detector.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
A 3-10 GHz, 14 Bands CMOS Frequency Synthesizer With Spurs Reduction for MB-OFDM UWB System.
IEEE Trans. Very Large Scale Integr. Syst., 2012

A 2.4 GHz Reference-Less Receiver for 1 Mbps QPSK Demodulation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A 160-GHz receiver-based phase-locked loop in 65 nm CMOS technology.
Proceedings of the Symposium on VLSI Circuits, 2012

A 40 Gbps optical receiver analog front-end in 65 nm CMOS.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
A 10-Gb/s OEIC with Meshed Spatially-Modulated Photo Detector in 0.18-μm CMOS Technology.
IEEE J. Solid State Circuits, 2011

Fast analog layout prototyping for nanometer design migration.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010
A 7.1 mW, 10 GHz All Digital Frequency Synthesizer With Dynamically Reconfigured Digital Loop Filter in 90 nm CMOS Technology.
IEEE J. Solid State Circuits, 2010

A 2.4 GHz reference-less wireless receiver for 1Mbps QPSK demodulation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
A Single-Chip 2.5-Gb/s CMOS Burst-Mode Optical Receiver.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

A 7.1mW 10GHz all-digital frequency synthesizer with dynamically reconfigurable digital loop filter in 90nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 10-Gbps CMOS single chip optical receiver with 2-D meshed spatially-modulated light detector.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
Low-Power Programmable Pseudorandom Word Generator and Clock Multiplier Unit for High-Speed SerDes Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

A 3-to-10GHz 14-Band CMOS Frequency Synthesizer with Spurs Reduction for MB-OFDM UWB System.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
A 90-dB Omega 10-Gb/s Optical Receiver Analog Front-End in a 0.18µm CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Three-Dimensional Fully Symmetric Inductors, Transformer, and Balun in CMOS Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

A 2.5 Gbps CMOS Fully Integrated Optical Receicer with Lateral PIN Detector.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Design and anaylsis of a 2.5-Gbps optical receiver analog front-end in a 0.35-μm digital CMOS technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

A low power programmable PRBS generator and a clock multiplier unit for 10 Gbps serdes applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end.
IEEE J. Solid State Circuits, 2005

Miniaturized 3-dimensional transformer design.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
A 2-V 2.3/4.6-GHz dual-band frequency synthesizer in 0.35-μm digital CMOS process.
IEEE J. Solid State Circuits, 2004

A 1.8 V, 10 Gbps fully integrated CMOS optical receiver analog front end.
Proceedings of the 33rd European Solid-State Circuits Conference, 2004

2003
10 GHz quadrature-phase voltage controlled oscillator and prescaler.
Proceedings of the ESSCIRC 2003, 2003

2002
A 2.5 Gbps CMOS optical receiver analog front-end.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

1999
A 2-V, 1.8-GHz BJT phase-locked loop.
IEEE J. Solid State Circuits, 1999

1998
A 2-V 2-GHz BJT variable frequency oscillator.
IEEE J. Solid State Circuits, 1998

A 2 V 1.6 GHz BJT phase-locked loop.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998


  Loading...