Ahmed Abdelaal

Orcid: 0000-0001-9724-5896

According to our database¹, Ahmed Abdelaal authored at least 17 papers between 2019 and 2026.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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Book In proceedings Article PhD thesis Dataset Other

Bibliography

2026

A Digitizing Integrator-Differentiator TIA With 1-MHz Bandwidth and 93-pA<sub>rms</sub> Sensitivity in 28-nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, June, 2026

2025

A 470- μ W, 102.6-dB DR, 20-kHz BW Calibration-Free ΔΣ Modulator With SFDR in Excess of 110 dBc Using an Intrinsically Linear 13-Level DAC.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, November, 2025

ΔΣ Modulators Employing MASH DSM DAC-Based Dual Quantization.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., January, 2025

PSumSim: A Simulator for Partial-Sum Quantization in Analog Matrix-Vector Multipliers.

[BibT_eX]

[DOI]

Vasileios Belagiannis

Maurits Ortmanns

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

Analysis of Dynamic Errors in Tri-level DACs for Continuous-Time Delta-Sigma Modulators.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

A Direct Digitizing, 1MHz Bandwidth, 28fA/√Hz Current Sensing Front-End Based on a Mixed-Signal Integrator-Differentiator TIA in 28nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

A Calibration-free 80MHz CT DSM Using Dual Quantization and ISI Shuffler Achieving 106.2dB SFDR.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

2024

A 600MS/s 10-bit SAR ADC with unit via-based delta-length C-DAC in 22nm FDSOI.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Using Negative-R Assisted Integrators in Wide-band Delta-Sigma Modulators.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023

A Chopped 6-bit 1.6 GS/s SAR ADC Utilizing Slow Decision Information in 22 nm FDSOI.

[BibT_eX]

[DOI]

Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2022

A 0.9-V DAC-Calibration-Free Continuous-Time Incremental Delta-Sigma Modulator Achieving 97-dB SFDR at 2 MS/s in 28-nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2022

2021

Influence of Excess Loop Delay on the STF of Continuous-Time Delta-Sigma Modulators.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

FIR Filter with Symmetric Non-Equal Coefficients for CT Delta-Sigma Modulators.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A 0.9-V Calibration-Free 97dB-SFDR 2-MS/s Continuous Time Incremental Delta-Sigma ADC Utilizing Variable Bit Width Quantizer in 28nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2020

FIR DACs in CT Incremental Delta-Sigma Modulators.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A Comparative Study of ISI Errors in Different DAC Structures for CT Delta-Sigma Modulators.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

Effective Filtering of Requantization Error in Dual Quantized CTDSM using FIR DAC.

[BibT_eX]

[DOI]

Ankesh Jain

Ahmed Abdelaal

Maurits Ortmanns

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Ahmed Abdelaal

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