Akihiko Yamada

According to our database, Akihiko Yamada authored at least 27 papers between 1974 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Iterative User Scheduling Method for MU-MIMO-OFDM Systems.

Akihiko Yamada, Satoshi Denno, Yafei Hou

Proceedings of the 12th IEEE Global Conference on Consumer Electronics, 2023

2019

2018 NEC C&C Prize Ceremony.

Akihiko Yamada

IEEE Ann. Hist. Comput., 2019

Parametron and Relay Computers Exhibition Held at Tokyo University of Science in November, 2018.

Akihiko Yamada

IEEE Ann. Hist. Comput., 2019

Remarks on the Design of First Digital Computers in Japan - Contributions of Yasuo Komamiya.

Radomir S. Stankovic, Tsutomu Sasao, Jaakko T. Astola, Akihiko Yamada

Proceedings of the Computer Aided Systems Theory - EUROCAST 2019, 2019

2018

IPSJ Certifies 100 IP Technology Heritage Artifacts in 10 Years.

Akihiko Yamada

IEEE Ann. Hist. Comput., 2018

2012

Events and Sightings.

Akihiko Yamada, Dag Spicer

IEEE Ann. Hist. Comput., 2012

2008

Events and Sightings.

Chigusa Kita, Thomas Haigh, Dag Spicer, Akihiko Yamada, Thomas J. Misa

IEEE Ann. Hist. Comput., 2008

Robust Face Recognition Based on Modified ICA without Training Sample of Test Subjects.

Xian-Hua Han, Yen-Wei Chen, Akihiko Yamada, Hideto Fujita

Proceedings of the 4th International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2008), 2008

2007

Events and Sightings.

Chigusa Kita, Dag Spicer, Anne Fitzpatrick, Akihiko Yamada

IEEE Ann. Hist. Comput., 2007

2006

Multi-subregion-based probabilistic approach to pose-invariant face recognition.

Akihiko Yamada, Takeo Kanade

Syst. Comput. Jpn., 2006

2003

Multi-subregion based probabilistic approach toward pose-invariant face recognition.

Takeo Kanade, Akihiko Yamada

Proceedings of the IEEE International Symposium on Computational Intelligence in Robotics and Automation: Computational Intelligence in Robotics and Automation for the New Millennium, 2003

1999

A design method of multidimensional linear-phase paraunitary filter banks with a lattice structure.

Shogo Muramatsu, Akihiko Yamada, Hitoshi Kiya

IEEE Trans. Signal Process., 1999

1998

A design method OF 2-D axial-symmetric paraunitary filter banks with a lattice structure.

Shogo Muramatsu, Akihiko Yamada, Hitoshi Kiya

Proceedings of the 9th European Signal Processing Conference, 1998

1996

A design method for oversampled paraunitary DFT filter banks using householder factorization.

K. Kajita, Hiroyuki Kobayashi, Shogo Muramatsu, Akihiko Yamada, Hitoshi Kiya

Proceedings of the 8th European Signal Processing Conference, 1996

1990

Challenge of design and test of ultra-large-scale circuits.

Akihiko Yamada

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

1989

Logic simulation engines in Japan.

Shigeru Takasaki, Fumiyasu Hirose, Akihiko Yamada

IEEE Des. Test, 1989

Scan design at NEC.

Shigehiro Funatsu, Masato Kawai, Akihiko Yamada

IEEE Des. Test, 1989

Design Automation for Large Mainframes and Supercomputers in NEC.

Akihiko Yamada

Proceedings of the Information Processing 89, Proceedings of the IFIP 11th World Computer Congress, San Francisco, USA, August 28, 1989

1982

MDS: An improved total system for firmware development.

Kazutoshi Takahashi, Etsuo Takahashi, Tatsushige Bitoh, Toshinori Aoyama, Akihiko Yamada

Proceedings of the 15th annual workshop on Microprogramming, 1982

Timing verification system based on delay time hierarchical nature.

Minoru Nomura, Shinichi Sato, Nobuo Takano, Toshinori Aoyama, Akihiko Yamada

Proceedings of the 19th Design Automation Conference, 1982

1981

A Calculus of Testability Measure at the Functional Level.

Shigeru Takasaki, Masato Kawai, Shigehiro Funatsu, Akihiko Yamada

Proceedings of the Proceedings International Test Conference 1981, 1981

Design automation status in Japan.

Akihiko Yamada

Proceedings of the 18th Design Automation Conference, 1981

Hierarchical design verification for large digital systems.

Tohru Sasaki, Akihiko Yamada, Toshinori Aoyama, Katsutoshi Hasegawa, Shunichi Kato, Shinichi Sato

Proceedings of the 18th Design Automation Conference, 1981

1980

MIXS: A mixed level simulator for large digital system logic verification.

Tohru Sasaki, Akihiko Yamada, Shunichi Kato, Terufumi Nakazawa, Kyoji Tomita, Nobuyoshi Nomizu

Proceedings of the 17th Design Automation Conference, 1980

1978

Automatic System Level Test Generation and Fault Location for Large Digital Systems.

Akihiko Yamada, Nobuo Wakatsuki, T. Fukui, Shigehiro Funatsu

Proceedings of the 15th Design Automation Conference, 1978

1977

Automatic test generation for large digital circuits.

Akihiko Yamada, Nobuo Wakatsuki, Hideo Shibano, Osamu Itoh, Kyoji Tomita, Shigehiro Funatsu

Proceedings of the 14th Design Automation Conference, 1977

1974

Microprogramming Design support System.

Akihiko Yamada, Akihiro Kawaguchi, Kazutoshi Takahashi, Shunichi Kato

Proceedings of the 11th Design Automation Workshop, 1974