Alan P. Su

Orcid: 0000-0002-5735-7700

According to our database1, Alan P. Su authored at least 13 papers between 2004 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2018
A Hybrid Multicast Routing Approach with Enhanced Methods for Mesh-Based Networks-on-Chip.
IEEE Trans. Computers, 2018

2017
A low power synthesis flow for multi-rate systems.
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

2012
Buffer size minimization method considering mix-clock domains and discontinuous data access.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011
A software/hardware co-debug platform for multi-core systems.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
A practice of ESL verification methodology from SystemC to FPGA: using EPC class-1 generation-2 RFID tag design as an example.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Application of ESL synthesis on GSM edge algorithm for base station.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
A low-cost SOC debug platform based on on-chip test architectures.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Transaction Level Modeling and Design Space Exploration for SOC Test Architectures.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
Fluidity concept for NoC: A congestion avoidance and relief routing scheme.
Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

Flow Maximization for NoC Routing Algorithms.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

2007
An architectural co-synthesis algorithm for energy-aware network-on-chip design.
Proceedings of the 2007 ACM Symposium on Applied Computing (SAC), 2007

2006
Applying ESL in A Dual-Core SoC Platform Designing.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

2004
Low Power Heuristic Block-level Voltage/Frequency Scheduling.
Proceedings of the International Conference on Embedded Systems and Applications, 2004


  Loading...