Fu-Lung Hsueh

According to our database1, Fu-Lung Hsueh authored at least 26 papers between 2007 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
A 0.66e<sub>rms</sub><sup>-</sup> Temporal-Readout-Noise 3-D-Stacked CMOS Image Sensor With Conditional Correlated Multiple Sampling Technique.
IEEE J. Solid State Circuits, 2018

2017
A Bluetooth Low-Energy Transceiver With 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching Network.
IEEE J. Solid State Circuits, 2017

2016
A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm.
IEEE J. Solid State Circuits, 2016

A Bluetooth low-energy (BLE) transceiver with TX/RX switchable on-chip matching network, 2.75mW high-IF discrete-time receiver, and 3.6mW all-digital transmitter.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2.1 An integrated 0.56THz frequency synthesizer with 21GHz locking range and -74dBc/Hz phase noise at 1MHz offset in 65nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

6.8 A 1.5V 33Mpixel 3D-stacked CMOS image sensor with negative substrate bias.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

F5: Advanced IC design for ultra-low-noise sensing.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

10.2 A 38mW 40Gb/s 4-lane tri-band PAM-4 / 16-QAM transceiver in 28nm CMOS for high-speed Memory interface.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
A 0.66e<sup>-</sup>rms temporal-readout-noise 3D-stacked CMOS image sensor with conditional correlated multiple sampling (CCMS) technique.
Proceedings of the Symposium on VLSI Circuits, 2015

14.9 Sub-sampling all-digital fractional-N frequency synthesizer with -111dBc/Hz in-band phase noise and an FOM of -242dB.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A fully integrated 28nm Bluetooth Low-Energy transmitter with 36% system efficiency at 3dBm.
Proceedings of the ESSCIRC Conference 2015, 2015

2014
A peripheral switchable 3D stacked CMOS image sensor.
Proceedings of the Symposium on VLSI Circuits, 2014

A 12mW all-digital PLL based on class-F DCO for 4G phones in 28nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2014

8.4 A 28Gb/s 1pJ/b shared-inductor optical receiver with 56% chip-area reduction in 28nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Session 11 overview: Emerging memory and wireless technology.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
An Embedded Dynamic Voltage Scaling (DVS) System Through 55 nm Single-Inductor Dual-Output (SIDO) Switching Converter for 12-Bit Video Digital-to-Analog Converter.
IEEE J. Solid State Circuits, 2012

Session 17 overview: Diagnostic and therapeutic technologies for health: Technology directions subcommittee.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 2.7GHz 3.9mW Mesh-BJT LC-VCO with -204dBc/Hz FOM in 65nm CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
55nm CMOS 12-bit 250MHz digital-to-analog converter with dynamic voltage scaling (DVS) technique through single-inductor dual-output (SIDO) converter.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

A 64-channel neuron recording system.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

Analysis and design of data transmission protocol for 1024-channel retinal prosthesis.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

2010
A V-band divide-by-three differential direct injection-locked frequency divider in 65-nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

A practice of ESL verification methodology from SystemC to FPGA: using EPC class-1 generation-2 RFID tag design as an example.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2007
A Low-Cost Triple-Channel 10-bit 250MHz DAC IP in 65nm CMOS Process.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007


  Loading...