Alexander Sprenger

Orcid: 0000-0002-0775-7677

According to our database1, Alexander Sprenger authored at least 5 papers between 2018 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2020
Logic Fault Diagnosis of Hidden Delay Defects.
Proceedings of the IEEE International Test Conference, 2020

Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

2019
Divide and Compact - Stochastic Space Compaction for Faster-than-at-Speed Test.
J. Circuits Syst. Comput., 2019

A Hybrid Space Compactor for Adaptive X-Handling.
Proceedings of the IEEE International Test Conference, 2019

2018
Tuning Stochastic Space Compaction to Faster-than-at-Speed Test.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018


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