Sybille Hellebrand

Orcid: 0000-0002-3717-3939

According to our database1, Sybille Hellebrand authored at least 72 papers between 1988 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
Robust Pattern Generation for Small Delay Faults Under Process Variations.
Proceedings of the IEEE International Test Conference, 2023

Approximate Communication: Balancing Performance, Power, Reliability, and Safety.
Proceedings of the IEEE European Test Symposium, 2023

Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication.
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023

Optimizing the Streaming of Sensor Data with Approximate Communication.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023

2021
Stress-Aware Periodic Test of Interconnects.
J. Electron. Test., 2021

2020
Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Logic Fault Diagnosis of Hidden Delay Defects.
Proceedings of the IEEE International Test Conference, 2020

Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

2019
Built-In Test for Hidden Delay Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Divide and Compact - Stochastic Space Compaction for Faster-than-at-Speed Test.
J. Circuits Syst. Comput., 2019

A Hybrid Space Compactor for Adaptive X-Handling.
Proceedings of the IEEE International Test Conference, 2019

2018
Design for Small Delay Test - A Simulation Study.
Microelectron. Reliab., 2018

Guest Editors' Introduction.
IEEE Embed. Syst. Lett., 2018

Tuning Stochastic Space Compaction to Faster-than-at-Speed Test.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

Extending Aging Monitors for Early Life and Wear-Out Failure Prevention.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017
Special session on early life failures.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Foreword.
Proceedings of the 22nd IEEE European Test Symposium, 2017

Design-for-FAST: Supporting X-tolerant compaction during Faster-than-at-Speed Test.
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

2016
X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed Test.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015
A High Performance SEU Tolerant Latch.
J. Electron. Test., 2015

Optimized Selection of Frequencies for Faster-Than-at-Speed Test.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014
SAT-based ATPG beyond stuck-at fault testing.
it Inf. Technol., 2014

Adaptive Bayesian Diagnosis of Intermittent Faults.
J. Electron. Test., 2014

FAST-BIST: Faster-than-at-Speed BIST targeting hidden delay defects.
Proceedings of the 2014 International Test Conference, 2014

2013
Analyzing and quantifying fault tolerance properties.
Proceedings of the 14th Latin American Test Workshop, 2013

2012
Built-in self-diagnosis targeting arbitrary defects with partial pseudo-exhaustive test.
Proceedings of the 13th Latin American Test Workshop, 2012

Built-in self-diagnosis exploiting strong diagnostic windows in mixed-mode test.
Proceedings of the 17th IEEE European Test Symposium, 2012

2011
Variation-aware fault modeling.
Sci. China Inf. Sci., 2011

Towards Variation-Aware Test Methods.
Proceedings of the 16th European Test Symposium, 2011

Diagnostic Test of Robust Circuits.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
Nano-electronic Systems (Nano-elektronische Systeme).
it Inf. Technol., 2010

Reusing NoC-infrastructure for test data compression.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Efficient test response compaction for robust BIST using parity sequences.
Proceedings of the 28th International Conference on Computer Design, 2010

Massive statistical process variations: A grand challenge for testing nanoelectronic circuits.
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2010), Chicago, Illinois, USA, June 28, 2010

The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

2009
ATPG-based grading of strong fault-secureness.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Are Robust Circuits Really Robust?
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008
Signature Rollback - A Technique for Testing Robust Circuits.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

A Modular Memory BIST for Optimized Memory Repair.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Verification and Analysis of Self-Checking Properties through ATPG.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

2007
An efficient fault tolerant mechanism to deal with permanent and transient failures in a network on chip.
Int. J. High Perform. Syst. Archit., 2007

An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy.
Proceedings of the 12th European Test Symposium, 2007

A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006
DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme (DFG-Project - Test and Reliability of Nano-Electronic Systems).
it Inf. Technol., 2006

2005
Low power embedded DRAMs with high quality error correcting capabilities.
Proceedings of the 10th European Test Symposium, 2005

2004
Data Compression for Multiple Scan Chains Using Dictionaries with Corrections.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003
A Hybrid Coding Strategy For Optimized Test Data Compression.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002
Efficient Online and Offline Testing of Embedded DRAMs.
IEEE Trans. Computers, 2002

A Mixed-Mode BIST Scheme Based on Folding Compression.
J. Comput. Sci. Technol., 2002

Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST.
J. Electron. Test., 2002

2001
A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters.
J. Electron. Test., 2001

1999
Error Detecting Refreshment for Embedded DRAMs.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms.
Proceedings of the Dependable Computing, 1999

Symmetric Transparent BIST for RAMs.
Proceedings of the 1999 Design, 1999

1998
Mixed-Mode BIST Using Embedded Processors.
J. Electron. Test., 1998

Synthesizing Fast, Online-Testable Control Units.
IEEE Des. Test Comput., 1998

Fast Self-Recovering Controllers.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs.
Proceedings of the 1998 Design, 1998

1997
STARBIST: Scan Autocorrelated Random Pattern Generation.
Proceedings of the 34st Conference on Design Automation, 1997

1995
Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers.
IEEE Trans. Computers, 1995

Pattern generation for a deterministic BIST scheme.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

1994
An efficient procedure for the synthesis of fast self-testable controller structures.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Synthesis of Self-Testable Controllers.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1992
The pseudoexhaustive test of sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1991
Synthese vollstaendig testbarer Schaltungen
PhD thesis, 1991

1990
Generating pseudo-exhaustive vectors for external testing.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

Tools and devices supporting the pseudo-exhaustive test.
Proceedings of the European Design Automation Conference, 1990

1989
The Pseudo-Exhaustive Test of Sequential Circuits.
Proceedings of the Proceedings International Test Conference 1989, 1989

1988
Automatisierung des Entwurfs vollständig testbarer Schaltungen.
Proceedings of the GI, 1988

Generating pattern sequences for the pseudo-exhaustive test of MOS-circuits.
Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988


  Loading...