Stefan Holst

According to our database1, Stefan Holst authored at least 45 papers between 1999 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
GPU-Accelerated Estimation and Targeted Reduction of Peak IR-Drop during Scan Chain Shifting.
IEICE Trans. Inf. Syst., October, 2023

Stock price movement prediction based on Stocktwits investor sentiment using FinBERT and ensemble SVM.
PeerJ Comput. Sci., 2023

Mitigating Test-Induced Yield-Loss by IR-Drop-Aware X-Filling.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

Exploiting the Error Resilience of the Preconditioned Conjugate Gradient Method for Energy and Delay Optimization.
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023

BiSTAHL: A Built-In Self-Testable Soft-Error-Hardened Scan-Cell.
Proceedings of the IEEE European Test Symposium, 2023

Guardband Optimization for the Preconditioned Conjugate Gradient Algorithm.
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023

2022
Evaluation and Test of Production Defects in Hardened Latches.
IEICE Trans. Inf. Syst., 2022

Power and Energy Safe Real-Time Multi-Core Task Scheduling.
Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022

On the Impact of Hardware Timing Errors on Stochastic Computing based Neural Networks.
Proceedings of the IEEE European Test Symposium, 2022

2021
On the Efficacy of Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption.
IEICE Trans. Inf. Syst., 2021

GPU-Accelerated Timing Simulation of Systolic-Array-Based AI Accelerators.
Proceedings of the 30th IEEE Asian Test Symposium, 2021

2020
Logic Fault Diagnosis of Hidden Delay Defects.
Proceedings of the IEEE International Test Conference, 2020

2019
Targeted Partial-Shift For Mitigating Shift Switching Activity Hot-Spots During Scan Test.
Proceedings of the 24th IEEE Pacific Rim International Symposium on Dependable Computing, 2019

Variation-Aware Small Delay Fault Diagnosis on Compressed Test Responses.
Proceedings of the IEEE International Test Conference, 2019

STAHL: A Novel Scan-Test-Aware Hardened Latch Design.
Proceedings of the 24th IEEE European Test Symposium, 2019

A Fault-Tolerant MPSoC For CubeSats.
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

2018
The impact of production defects on the soft-error tolerance of hardened latches.
Proceedings of the 23rd IEEE European Test Symposium, 2018

Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017
GPU-Accelerated Simulation of Small Delay Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Analysis and mitigation or IR-Drop induced scan shift-errors.
Proceedings of the IEEE International Test Conference, 2017

Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption.
Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016
Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015
High-Throughput Logic Timing Simulation on GPGPUs.
ACM Trans. Design Autom. Electr. Syst., 2015

A soft-error tolerant TCAM using partial don't-care keys.
Proceedings of the 20th IEEE European Test Symposium, 2015

GPU-accelerated small delay fault simulation.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014
On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST.
IEICE Trans. Inf. Syst., 2014

Data-parallel simulation for fast and accurate timing validation of CMOS circuits.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Soft-error tolerant TCAMs for high-reliability packet classifications.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2012
Efficient location-based logic diagnosis of digital circuits.
PhD thesis, 2012

Structural Test and Diagnosis for Graceful Degradation of NoC Switches.
J. Electron. Test., 2012

Acceleration of Monte-Carlo molecular simulations on hybrid computing architectures.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Scan Test Power Simulation on GPGPUs.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011
Structural Test for Graceful Degradation of NoC Switches.
Proceedings of the 16th European Test Symposium, 2011

Embedded Test for Highly Accurate Defect Localization.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2009
Adaptive Debug and Diagnosis Without Fault Dictionaries.
J. Electron. Test., 2009

Restrict Encoding for Mixed-Mode BIST.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Test Encoding for Extreme Response Compaction.
Proceedings of the 14th IEEE European Test Symposium, 2009

A diagnosis algorithm for extreme space compaction.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
An a priori error estimate for a monotone mixed finite-element discretization of a convection-diffusion problem.
Numerische Mathematik, 2008

2004
An Adaptive Mixed Scheme for Energy-Transport Simulations of Field-Effect Transistors.
SIAM J. Sci. Comput., 2004

2003
A Mixed Finite-Element Discretization of the Energy-Transport Model for Semiconductors.
SIAM J. Sci. Comput., 2003

1999
Realization of an Agent-Based Certificate Authority and Key Distribution.
Proceedings of the Intelligent Agents for Telecommunication Applications, 1999


  Loading...