Xiaoqing Wen

According to our database1, Xiaoqing Wen authored at least 135 papers between 1990 and 2019.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2012, "For contributions to testing of integrated circuits".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. VLSI Syst., 2019

Novel Double-Node-Upset-Tolerant Memory Cell Designs Through Radiation-Hardening-by-Design and Layout.
IEEE Trans. Reliability, 2019

A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application.
IEEE Trans. on Circuits and Systems, 2019

STAHL: A Novel Scan-Test-Aware Hardened Latch Design.
Proceedings of the 24th IEEE European Test Symposium, 2019

Single-Event Double-Upset Self-Recoverable and Single-Event Transient Pulse Filterable Latch Design for Low Power Applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
A Method to Detect Bit Flips in a Soft-Error Resilient TCAM.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

The impact of production defects on the soft-error tolerance of hardened latches.
Proceedings of the 23rd IEEE European Test Symposium, 2018

2017
Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding.
IEEE Trans. VLSI Syst., 2017

Editorial.
IEEE Trans. VLSI Syst., 2017

GPU-Accelerated Simulation of Small Delay Faults.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Vernier ring based pre-bond through silicon vias test in 3D ICs.
IEICE Electronic Express, 2017

Analysis and mitigation or IR-Drop induced scan shift-errors.
Proceedings of the IEEE International Test Conference, 2017

Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption.
Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016
Test Pattern Modification for Average IR-Drop Reduction.
IEEE Trans. VLSI Syst., 2016

Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation.
IEICE Transactions, 2016

Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures.
IEICE Transactions, 2016

Multiple-Bit-Flip Detection Scheme for a Soft-Error Resilient TCAM.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

SAT-based post-processing for regional capture power reduction in at-speed scan test generation.
Proceedings of the 21th IEEE European Test Symposium, 2016

On Optimal Power-Aware Path Sensitization.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015
A soft-error tolerant TCAM using partial don't-care keys.
Proceedings of the 20th IEEE European Test Symposium, 2015

Identification of high power consuming areas with gate type and logic level information.
Proceedings of the 20th IEEE European Test Symposium, 2015

GPU-accelerated small delay fault simulation.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

Power supply noise and its reduction in at-speed scan testing.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST.
IEICE Transactions, 2014

Pattern analysis of a modified Leslie-Gower predator-prey model with Crowley-Martin functional response and diffusion.
Computers & Mathematics with Applications, 2014

Data-parallel simulation for fast and accurate timing validation of CMOS circuits.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Soft-error tolerant TCAMs for high-reliability packet classifications.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
Stability of regulatory protein Gradients induced by morphogen DPP in Drosophila wing Disc.
I. J. Bifurcation and Chaos, 2013

A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing.
IEICE Transactions, 2013

LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing.
IEEE Design & Test, 2013

On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST.
Proceedings of the 22nd Asian Test Symposium, 2013

Search Space Reduction for Low-Power Test Generation.
Proceedings of the 22nd Asian Test Symposium, 2013

2012
Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains.
ACM Trans. Design Autom. Electr. Syst., 2012

Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of Transition Delay Fault Patterns.
J. Low Power Electronics, 2012

A novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuits.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

On pinpoint capture power management in at-speed scan test generation.
Proceedings of the 2012 IEEE International Test Conference, 2012

Power-aware testing: The next stage.
Proceedings of the 17th IEEE European Test Symposium, 2012

Session Summary III: Power-Aware Testing: Present and Future.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

A Transition Isolation Scan Cell Design for Low Shift and Capture Power.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011
Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing.
IEICE Transactions, 2011

Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing.
IEICE Transactions, 2011

Special session 5B: Panel How much toggle activity should we be testing with?
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Power-aware test generation with guaranteed launch safety for at-speed scan testing.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

A novel scan segmentation design method for avoiding shift timing failure in scan testing.
Proceedings of the 2011 IEEE International Test Conference, 2011

Clock-gating-aware low launch WSA test pattern generation for at-speed scan testing.
Proceedings of the 2011 IEEE International Test Conference, 2011

SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

VLSI testing and test power.
Proceedings of the 2011 International Green Computing Conference and Workshops, 2011

Transition-Time-Relation based capture-safety checking for at-speed scan test generation.
Proceedings of the Design, Automation and Test in Europe, 2011

Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Efficient BDD-based Fault Simulation in Presence of Unknown Values.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Towards the next generation of low-power test technologies.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes.
J. Low Power Electronics, 2010

On Delay Test Quality for Test Cubes.
IPSJ Trans. System LSI Design Methodology, 2010

A Study of Capture-Safe Test Generation Flow for At-Speed Testing.
IEICE Transactions, 2010

High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme.
IEICE Transactions, 2010

Is test power reduction through X-filling good enough?
Proceedings of the 2011 IEEE International Test Conference, 2010

On estimation of NBTI-Induced delay degradation.
Proceedings of the 15th European Test Symposium, 2010

Case Studies on Transition Fault Test Generation for At-speed Scan Testing.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

Hybrid Built-In Self-Test Architecture for Multi-port Static RAMs.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

Low-Power Testing for Low-Power Devices.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2009
Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Turbo1500: Core-Based Design for Test and Diagnosis.
IEEE Design & Test of Computers, 2009

A GA-Based Method for High-Quality X-Filling to Reduce Launch Switching Activity in At-speed Scan Testing.
Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
Test Strategies for Low-Power Devices.
J. Low Power Electronics, 2008

Estimation of Delay Test Quality and Its Application to Test Generation.
IPSJ Trans. System LSI Design Methodology, 2008

A Novel Per-Test Fault Diagnosis Method Based on the Extended X-Fault Model for Deep-Submicron LSI Circuits.
IEICE Transactions, 2008

On Detection of Bridge Defects with Stuck-at Tests.
IEICE Transactions, 2008

Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing.
J. Electronic Testing, 2008

VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG.
IEEE Design & Test of Computers, 2008

Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Scan Testing.
Proceedings of the 2008 IEEE International Test Conference, 2008

Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard.
Proceedings of the 2008 IEEE International Test Conference, 2008

Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

A Capture-Safe Test Generation Scheme for At-Speed Scan Testing.
Proceedings of the 13th European Test Symposium, 2008

On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Diagnosis of Realistic Defects Based on the X-Fault Model.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Test Strategies for Low Power Devices.
Proceedings of the Design, Automation and Test in Europe, 2008

Power-Aware Testing and Test Strategies for Low Power Devices.
Proceedings of the Design, Automation and Test in Europe, 2008

Practical Challenges in Logic BIST Implementation.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007
A Novel ATPG Method for Capture Power Reduction during Scan Testing.
IEICE Transactions, 2007

At-Speed Logic BIST for IP Cores
CoRR, 2007

A novel scheme to reduce power supply noise for high-quality at-speed scan testing.
Proceedings of the 2007 IEEE International Test Conference, 2007

Estimation of delay test quality and its application to test generation.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Embedded Tutorial on Low Power Test.
Proceedings of the 12th European Test Symposium, 2007

Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing.
Proceedings of the 44th Design Automation Conference, 2007

2006
A New Method for Low-Capture-Power Test Generation for Scan Testing.
IEICE Transactions, 2006

A Per-Test Fault Diagnosis Method Based on the X-Fault Model.
IEICE Transactions, 2006

Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time.
IEICE Transactions, 2006

A New ATPG Method for Efficient Capture Power Reduction During Scan Testing.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

A Framework of High-quality Transition Fault ATPG for Scan Circuits.
Proceedings of the 2006 IEEE International Test Conference, 2006

A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing.
Proceedings of the 2006 IEEE International Test Conference, 2006

Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

A dynamic test compaction procedure for high-quality path delay testing.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Efficient Test Set Modification for Capture Power Reduction.
J. Low Power Electronics, 2005

Fault Diagnosis of Physical Defects Using Unknown Behavior Model.
J. Comput. Sci. Technol., 2005

On Design for IDDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies.
IEICE Transactions, 2005

Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores.
IEICE Transactions, 2005

On Low-Capture-Power Test Generation for Scan Testing.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time.
Proceedings of the 11th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2005), 2005

Low-capture-power test generation for scan-based at-speed testing.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

UltraScan: using time-division demultiplexing/multiplexing (TDDM/TDM) with VirtualScan for test cost reduction.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

At-Speed Logic BIST Architecture for Multi-Clock Designs.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

At-Speed Logic BIST for IP Cores.
Proceedings of the 2005 Design, 2005

Path delay test compaction with process variation tolerance.
Proceedings of the 42nd Design Automation Conference, 2005

On Improving Defect Coverage of Stuck-at Fault Tests.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
VirtualScan: A New Compressed Scan Technology for Test Cost Reduction.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

On per-test fault diagnosis using the X-fault model.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

2003
Fault Diagnosis for Physical Defects of Unknown Behaviors.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2001
A Flexible Logic BIST Scheme and Its Application to SoC Designs.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

1999
Random pattern testable design with partial circuit duplication and IDDQ testing.
Systems and Computers in Japan, 1999

1998
Design for Diagnosability of CMOS Circuits.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997
IDDQ test vector selection for transistor short fault testing.
Systems and Computers in Japan, 1997

Random Pattern Testable Design with Partial Circuit Duplication.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

Fault Diagnosis for Static CMOS Circuits.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996
A new method towards achieving global optimality in technology mapping.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

1995
Testing of k-FR Circuits under Highly Observable Condition.
IEICE Transactions, 1995

Efficient Guided-Probe Fault Location Method for Sequential Circuits.
IEICE Transactions, 1995

Transistor leakage fault location with ZDDQ measurement.
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1992
A Testable Design of Logic Circuits under Highly Observable Condition.
IEEE Trans. Computers, 1992

Testable Designs of Sequential Circuits Under Highly Observable Condition.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1990
A testable design of logic circuits under highly observable condition.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

Fault detection and diagnosis of k-UCP circuits under totally observable condition.
Proceedings of the 20th International Symposium on Fault-Tolerant Computing, 1990


  Loading...