Xiaoqing Wen

According to our database1, Xiaoqing Wen authored at least 223 papers between 1990 and 2024.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2012, "For contributions to testing of integrated circuits".

Timeline

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Bibliography

2024
Comprehensive and Comparative Analysis of QCA-based Circuit Designs for Next-generation Computation.
ACM Comput. Surv., May, 2024

Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS.
IEEE Trans. Very Large Scale Integr. Syst., January, 2024

Introduction to the Special Issue on Design for Testability and Reliability of Security-aware Hardware.
ACM Trans. Design Autom. Electr. Syst., January, 2024

2023
RMC_NoC: A Reliable On-Chip Network Architecture With Reconfigurable Multifunctional Channel.
IEEE Trans. Very Large Scale Integr. Syst., December, 2023

Design of True Random Number Generator Based on Multi-Ring Convergence Oscillator Using Short Pulse Enhanced Randomness.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

An AI-Driven VM Threat Prediction Model for Multi-Risks Analysis-Based Cloud Cybersecurity.
IEEE Trans. Syst. Man Cybern. Syst., November, 2023

GPU-Accelerated Estimation and Targeted Reduction of Peak IR-Drop during Scan Chain Shifting.
IEICE Trans. Inf. Syst., October, 2023

An equivalent processing method for integrated circuit electrical parameter data using BP neural networks.
Microelectron. J., September, 2023

Two sextuple cross-coupled SRAM cells with double-node-upset protection and cost optimization for aerospace applications.
Microelectron. J., September, 2023

A Highly Robust and Low-Power Flip-Flop Cell With Complete Double-Node-Upset Tolerance for Aerospace Applications.
IEEE Des. Test, August, 2023

Designs of BCD Adder Based on Excess-3 Code in Quantum-Dot Cellular Automata.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023

LDAVPM: A Latch Design and Algorithm-Based Verification Protected Against Multiple-Node-Upsets in Harsh Radiation Environments.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2023

Designs of Two Quadruple-Node-Upset Self-Recoverable Latches for Highly Robust Computing in Harsh Radiation Environments.
IEEE Trans. Aerosp. Electron. Syst., June, 2023

Energy-Efficient Multiple Network-on-Chip Architecture With Bandwidth Expansion.
IEEE Trans. Very Large Scale Integr. Syst., April, 2023

Two Double-Node-Upset-Hardened Flip-Flop Designs for High-Performance Applications.
IEEE Trans. Emerg. Top. Comput., 2023

Trusted fingerprint localization for multimedia devices based on blockchain.
Inf. Sci., 2023

Mitigating Test-Induced Yield-Loss by IR-Drop-Aware X-Filling.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

Design of a Novel Latch with Quadruple-Node-Upset Recovery for Harsh Radiation Hardness.
Proceedings of the IEEE International Test Conference in Asia, 2023

A Low Overhead and Double-Node-Upset Self-Recoverable Latch.
Proceedings of the IEEE International Test Conference in Asia, 2023

Design of A Highly Reliable and Low-Power SRAM With Double-Node Upset Recovery for Safety-critical Applications.
Proceedings of the IEEE International Test Conference in Asia, 2023

Design of Low-Cost Approximate CMOS Full Adders.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A Low Area and Low Delay Latch Design with Complete Double-Node-Upset-Recovery for Aerospace Applications.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

Two Highly Reliable and High-Speed SRAM Cells for Safety-Critical Applications.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

BiSTAHL: A Built-In Self-Testable Soft-Error-Hardened Scan-Cell.
Proceedings of the IEEE European Test Symposium, 2023

A Robust and High-Performance Flip-Flop with Complete Soft-Error Recovery.
Proceedings of the 10th International Conference on Dependable Systems and Their Applications, 2023

SASL-JTAG: A Light-Weight Dependable JTAG.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

High Performance and DNU-Recovery Spintronic Retention Latch for Hybrid MTJ/CMOS Technology.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Advanced DICE Based Triple-Node-Upset Recovery Latch with Optimized Overhead for Space Applications.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023

A High-Performance and P-Type FeFET-Based Non-Volatile Latch.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023

Enhancing Defect Diagnosis and Localization in Wafer Map Testing Through Weakly Supervised Learning.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023

A Lightweight and Machine-Learning-Resistant PUF framework based on Nonlinear Structure and Obfuscating Challenges.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2023

2022
Novel Quadruple-Node-Upset-Tolerant Latch Designs With Optimized Overhead for Reliable Computing in Harsh Radiation Environments.
IEEE Trans. Emerg. Top. Comput., 2022

Cellular Structure-Based Fault-Tolerance TSV Configuration in 3D-IC.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Fortune: A New Fault-Tolerance TSV Configuration in Router-Based Redundancy Structure.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

GoodFloorplan: Graph Convolutional Network and Reinforcement Learning-Based Floorplanning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Cost-Effective and Highly Reliable Circuit-Components Design for Safety-Critical Applications.
IEEE Trans. Aerosp. Electron. Syst., 2022

A Secure and Multiobjective Virtual Machine Placement Framework for Cloud Data Center.
IEEE Syst. J., 2022

A double-node-upset completely tolerant CMOS latch design with extremely low cost for high-performance applications.
Integr., 2022

Evaluation and Test of Production Defects in Hardened Latches.
IEICE Trans. Inf. Syst., 2022

Broadcast-TDMA: A Cost-Effective Fault-Tolerance Method for TSV Lifetime Reliability Enhancement.
IEEE Des. Test, 2022

A Highly Reliable and Low Power RHBD Flip-Flop Cell for Aerospace Applications.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022

Power and Energy Safe Real-Time Multi-Core Task Scheduling.
Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022

Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOS.
Proceedings of the IEEE International Test Conference in Asia, 2022

Effective Switching Probability Calculation to Locate Hotspots in Logic Circuits.
Proceedings of the IEEE International Test Conference in Asia, 2022

A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS Technology.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

Two 0.8 V, Highly Reliable RHBD 10T and 12T SRAM Cells for Aerospace Applications.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

Sextuple Cross-Coupled-DICE Based Double-Node-Upset Recoverable and Low-Delay Flip-Flop for Aerospace Applications.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

SCLCRL: Shuttling C-elements based Low-Cost and Robust Latch Design Protected against Triple Node Upsets in Harsh Radiation Environments.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

A Radiation-Hardened Non-Volatile Magnetic Latch with High Reliability and Persistent Storage.
Proceedings of the IEEE 31st Asian Test Symposium, 2022

MRCO: A Multi-ring Convergence Oscillator-based High-Efficiency True Random Number Generator.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2022

2021
Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS.
IEEE Trans. Emerg. Top. Comput., 2021

A Novel TDMA-Based Fault Tolerance Technique for the TSVs in 3D-ICs Using Honeycomb Topology.
IEEE Trans. Emerg. Top. Comput., 2021

A Cost-Effective TSV Repair Architecture for Clustered Faults in 3-D IC.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications.
Microelectron. J., 2021

On the Efficacy of Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption.
IEICE Trans. Inf. Syst., 2021

Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications.
J. Electron. Test., 2021

A Secure and Multi-objective Virtual Machine Placement Framework for Cloud Data Centre.
CoRR, 2021

A Sextuple Cross-Coupled Dual-Interlocked-Storage-Cell based Multiple-Node-Upset Self-Recoverable Latch.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021

Parallel DICE Cells and Dual-Level CEs based 3-Node-Upset Tolerant Latch Design for Highly Robust Computing.
Proceedings of the IEEE International Test Conference in Asia, 2021

A Blockchain-based Verified Locating Scheme for IoT Devices.
Proceedings of the 2021 IEEE Intl Conf on Parallel & Distributed Processing with Applications, Big Data & Cloud Computing, Sustainable Computing & Communications, Social Computing & Networking (ISPA/BDCloud/SocialCom/SustainCom), New York City, NY, USA, September 30, 2021

TPDICE and Sim Based 4-Node-Upset Completely Hardened Latch Design for Highly Robust Computing in Harsh Radiation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A 4NU-Recoverable and HIS-Insensitive Latch Design for Highly Robust Computing in Harsh Radiation Environments.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

A Reliable and Low-Cost Flip-Flop Hardened against Double-Node-Upsets.
Proceedings of the 8th International Conference on Dependable Systems and Their Applications, 2021

Reliability-Driven Neuromorphic Computing Systems Design.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

A Blockchain-based Framework for Information Management in Internet of Vehicles.
Proceedings of the 8th IEEE International Conference on Cyber Security and Cloud Computing, 2021

GPU-Accelerated Timing Simulation of Systolic-Array-Based AI Accelerators.
Proceedings of the 30th IEEE Asian Test Symposium, 2021

LSI Testing: A Core Technology to a Successful LSI Industry.
Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020
A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips.
IEEE Trans. Emerg. Top. Comput., 2020

Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells-Based Multiple-Node-Upset-Tolerant Latch Designs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Novel Speed-and-Power-Optimized SRAM Cell Designs With Enhanced Self-Recoverability From Single- and Double-Node Upsets.
IEEE Trans. Circuits Syst., 2020

Non-Intrusive Online Distributed Pulse Shrinking-Based Interconnect Testing in 2.5D IC.
IEEE Trans. Circuits Syst., 2020

LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Information Assurance Through Redundant Design: A Novel TNU Error-Resilient Latch for Harsh Radiation Environment.
IEEE Trans. Computers, 2020

A Novel Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Aerospace Applications.
IEEE Trans. Aerosp. Electron. Syst., 2020

Design of a Triple-Node-Upset Self-Recoverable Latch for Aerospace Applications in Harsh Radiation Environments.
IEEE Trans. Aerosp. Electron. Syst., 2020

Design of Double-Upset Recoverable and Transient-Pulse Filterable Latches for Low-Power and Low-Orbit Aerospace Applications.
IEEE Trans. Aerosp. Electron. Syst., 2020

Logic Fault Diagnosis of Hidden Delay Defects.
Proceedings of the IEEE International Test Conference, 2020

Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft Errors.
Proceedings of the IEEE International Test Conference in Asia, 2020

Dual-Interlocked-Storage-Cell-Based Double-Node-Upset Self-Recoverable Flip-Flop Design for Safety-Critical Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

HITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filterable Latch for Safety-Critical Applications.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

A Sextuple Cross-Coupled SRAM Cell Protected against Double-Node Upsets.
Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Novel Double-Node-Upset-Tolerant Memory Cell Designs Through Radiation-Hardening-by-Design and Layout.
IEEE Trans. Reliab., 2019

A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Novel Quadruple Cross-Coupled Memory Cell Designs With Protection Against Single Event Upsets and Double-Node Upsets.
IEEE Access, 2019

Targeted Partial-Shift For Mitigating Shift Switching Activity Hot-Spots During Scan Test.
Proceedings of the 24th IEEE Pacific Rim International Symposium on Dependable Computing, 2019

Variation-Aware Small Delay Fault Diagnosis on Compressed Test Responses.
Proceedings of the IEEE International Test Conference, 2019

A Novel Triple-Node-Upset-Tolerant CMOS Latch Design using Single-Node-Upset-Resilient Cells.
Proceedings of the IEEE International Test Conference in Asia, 2019

A Static Method for Analyzing Hotspot Distribution on the LSI.
Proceedings of the IEEE International Test Conference in Asia, 2019

STAHL: A Novel Scan-Test-Aware Hardened Latch Design.
Proceedings of the 24th IEEE European Test Symposium, 2019

A Fault-Tolerant MPSoC For CubeSats.
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

Single-Event Double-Upset Self-Recoverable and Single-Event Transient Pulse Filterable Latch Design for Low Power Applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Design of a Sextuple Cross-Coupled SRAM Cell with Optimized Access Operations for Highly Reliable Terrestrial Applications.
Proceedings of the 28th IEEE Asian Test Symposium, 2019

Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications.
Proceedings of the 28th IEEE Asian Test Symposium, 2019

2018
A Method to Detect Bit Flips in a Soft-Error Resilient TCAM.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

The impact of production defects on the soft-error tolerance of hardened latches.
Proceedings of the 23rd IEEE European Test Symposium, 2018

Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017
Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Editorial.
IEEE Trans. Very Large Scale Integr. Syst., 2017

GPU-Accelerated Simulation of Small Delay Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Vernier ring based pre-bond through silicon vias test in 3D ICs.
IEICE Electron. Express, 2017

Analysis and mitigation or IR-Drop induced scan shift-errors.
Proceedings of the IEEE International Test Conference, 2017

Scan Chain Grouping for Mitigating IR-Drop-Induced Test Data Corruption.
Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016
Test Pattern Modification for Average IR-Drop Reduction.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

Reseeding-Oriented Test Power Reduction for Linear-Decompression-Based Test Compression Architectures.
IEICE Trans. Inf. Syst., 2016

Multiple-Bit-Flip Detection Scheme for a Soft-Error Resilient TCAM.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

SAT-based post-processing for regional capture power reduction in at-speed scan test generation.
Proceedings of the 21th IEEE European Test Symposium, 2016

On Optimal Power-Aware Path Sensitization.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015
A soft-error tolerant TCAM using partial don't-care keys.
Proceedings of the 20th IEEE European Test Symposium, 2015

Identification of high power consuming areas with gate type and logic level information.
Proceedings of the 20th IEEE European Test Symposium, 2015

GPU-accelerated small delay fault simulation.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

Power supply noise and its reduction in at-speed scan testing.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST.
IEICE Trans. Inf. Syst., 2014

Pattern analysis of a modified Leslie-Gower predator-prey model with Crowley-Martin functional response and diffusion.
Comput. Math. Appl., 2014

Data-parallel simulation for fast and accurate timing validation of CMOS circuits.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Soft-error tolerant TCAMs for high-reliability packet classifications.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
Stability of regulatory protein Gradients induced by morphogen DPP in <i>Drosophila</i> wing Disc.
Int. J. Bifurc. Chaos, 2013

A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing.
IEICE Trans. Inf. Syst., 2013

LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing.
IEEE Des. Test, 2013

On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST.
Proceedings of the 22nd Asian Test Symposium, 2013

Search Space Reduction for Low-Power Test Generation.
Proceedings of the 22nd Asian Test Symposium, 2013

2012
Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains.
ACM Trans. Design Autom. Electr. Syst., 2012

Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of Transition Delay Fault Patterns.
J. Low Power Electron., 2012

A novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuits.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

On pinpoint capture power management in at-speed scan test generation.
Proceedings of the 2012 IEEE International Test Conference, 2012

Power-aware testing: The next stage.
Proceedings of the 17th IEEE European Test Symposium, 2012

Session Summary III: Power-Aware Testing: Present and Future.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

A Transition Isolation Scan Cell Design for Low Shift and Capture Power.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011
Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

A GA-Based <i>X</i>-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing.
IEICE Trans. Inf. Syst., 2011

Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing.
IEICE Trans. Inf. Syst., 2011

Special session 5B: Panel How much toggle activity should we be testing with?
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Power-aware test generation with guaranteed launch safety for at-speed scan testing.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

A novel scan segmentation design method for avoiding shift timing failure in scan testing.
Proceedings of the 2011 IEEE International Test Conference, 2011

Clock-gating-aware low launch WSA test pattern generation for at-speed scan testing.
Proceedings of the 2011 IEEE International Test Conference, 2011

SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

VLSI testing and test power.
Proceedings of the 2011 International Green Computing Conference and Workshops, 2011

Transition-Time-Relation based capture-safety checking for at-speed scan test generation.
Proceedings of the Design, Automation and Test in Europe, 2011

Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Efficient BDD-based Fault Simulation in Presence of Unknown Values.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Power-Aware Test Pattern Generation for At-Speed LOS Testing.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Towards the next generation of low-power test technologies.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes.
J. Low Power Electron., 2010

On Delay Test Quality for Test Cubes.
IPSJ Trans. Syst. LSI Des. Methodol., 2010

A Study of Capture-Safe Test Generation Flow for At-Speed Testing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme.
IEICE Trans. Inf. Syst., 2010

Is test power reduction through X-filling good enough?
Proceedings of the 2011 IEEE International Test Conference, 2010

On estimation of NBTI-Induced delay degradation.
Proceedings of the 15th European Test Symposium, 2010

Case Studies on Transition Fault Test Generation for At-speed Scan Testing.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

Hybrid Built-In Self-Test Architecture for Multi-port Static RAMs.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

Low-Power Testing for Low-Power Devices.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2009
Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Turbo1500: Core-Based Design for Test and Diagnosis.
IEEE Des. Test Comput., 2009

A GA-Based Method for High-Quality X-Filling to Reduce Launch Switching Activity in At-speed Scan Testing.
Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
Test Strategies for Low-Power Devices.
J. Low Power Electron., 2008

Estimation of Delay Test Quality and Its Application to Test Generation.
IPSJ Trans. Syst. LSI Des. Methodol., 2008

A Novel Per-Test Fault Diagnosis Method Based on the Extended <i>X</i>-Fault Model for Deep-Submicron LSI Circuits.
IEICE Trans. Inf. Syst., 2008

On Detection of Bridge Defects with Stuck-at Tests.
IEICE Trans. Inf. Syst., 2008

Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing.
J. Electron. Test., 2008

VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG.
IEEE Des. Test Comput., 2008

Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Scan Testing.
Proceedings of the 2008 IEEE International Test Conference, 2008

Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard.
Proceedings of the 2008 IEEE International Test Conference, 2008

Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

A Capture-Safe Test Generation Scheme for At-Speed Scan Testing.
Proceedings of the 13th European Test Symposium, 2008

On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Diagnosis of Realistic Defects Based on the X-Fault Model.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Power-Aware Testing and Test Strategies for Low Power Devices.
Proceedings of the Design, Automation and Test in Europe, 2008

Practical Challenges in Logic BIST Implementation.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007
A Novel ATPG Method for Capture Power Reduction during Scan Testing.
IEICE Trans. Inf. Syst., 2007

A novel scheme to reduce power supply noise for high-quality at-speed scan testing.
Proceedings of the 2007 IEEE International Test Conference, 2007

Embedded Tutorial on Low Power Test.
Proceedings of the 12th European Test Symposium, 2007

Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing.
Proceedings of the 44th Design Automation Conference, 2007

2006
A New Method for Low-Capture-Power Test Generation for Scan Testing.
IEICE Trans. Inf. Syst., 2006

A Per-Test Fault Diagnosis Method Based on the <i>X</i>-Fault Model.
IEICE Trans. Inf. Syst., 2006

Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time.
IEICE Trans. Inf. Syst., 2006

A New ATPG Method for Efficient Capture Power Reduction During Scan Testing.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

A Framework of High-quality Transition Fault ATPG for Scan Circuits.
Proceedings of the 2006 IEEE International Test Conference, 2006

A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing.
Proceedings of the 2006 IEEE International Test Conference, 2006

Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Test data compression based on clustered random access scan.
Proceedings of the 15th Asian Test Symposium, 2006

A dynamic test compaction procedure for high-quality path delay testing.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Efficient Test Set Modification for Capture Power Reduction.
J. Low Power Electron., 2005

Fault Diagnosis of Physical Defects Using Unknown Behavior Model.
J. Comput. Sci. Technol., 2005

On Design for I<sub>DDQ</sub>-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies.
IEICE Trans. Inf. Syst., 2005

Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores.
IEICE Trans. Inf. Syst., 2005

On Low-Capture-Power Test Generation for Scan Testing.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time.
Proceedings of the 11th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2005), 2005

Low-capture-power test generation for scan-based at-speed testing.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

UltraScan: using time-division demultiplexing/multiplexing (TDDM/TDM) with VirtualScan for test cost reduction.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

At-Speed Logic BIST Architecture for Multi-Clock Designs.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

At-Speed Logic BIST for IP Cores.
Proceedings of the 2005 Design, 2005

Path delay test compaction with process variation tolerance.
Proceedings of the 42nd Design Automation Conference, 2005

On Improving Defect Coverage of Stuck-at Fault Tests.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
VirtualScan: A New Compressed Scan Technology for Test Cost Reduction.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

On per-test fault diagnosis using the X-fault model.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

2003
Fault Diagnosis for Physical Defects of Unknown Behaviors.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2001
A Flexible Logic BIST Scheme and Its Application to SoC Designs.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

1999
Random pattern testable design with partial circuit duplication and I<sub>DDQ</sub> testing.
Syst. Comput. Jpn., 1999

1998
Design for Diagnosability of CMOS Circuits.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997
I<sub>DDQ</sub> test vector selection for transistor short fault testing.
Syst. Comput. Jpn., 1997

Random Pattern Testable Design with Partial Circuit Duplication.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

Fault Diagnosis for Static CMOS Circuits.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996
A new method towards achieving global optimality in technology mapping.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

1995
Testing of <i>k</i>-FR Circuits under Highly Observable Condition.
IEICE Trans. Inf. Syst., 1995

Efficient Guided-Probe Fault Location Method for Sequential Circuits.
IEICE Trans. Inf. Syst., 1995

Transistor leakage fault location with ZDDQ measurement.
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1992
A Testable Design of Logic Circuits under Highly Observable Condition.
IEEE Trans. Computers, 1992

Testable Designs of Sequential Circuits Under Highly Observable Condition.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1990
Fault detection and diagnosis of k-UCP circuits under totally observable condition.
Proceedings of the 20th International Symposium on Fault-Tolerant Computing, 1990


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