Jan Dennis Reimer

According to our database, Jan Dennis Reimer authored at least 7 papers between 2020 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

Validating Statistical Delay Test Generation Under Timing Variations via SAT-Based ATPG.

Hanieh Jafarzadeh, Jan Dennis Reimer, Hussam Amrouch, Sybille Hellebrand, Hans-Joachim Wunderlich

Proceedings of the 27th IEEE Latin American Test Symposium, 2026

2024

Minimizing PVT-Variability by Exploiting the Zero Temperature Coefficient (ZTC) for Robust Delay Fault Testing.

Hanieh Jafarzadeh, Florian Klemme, Jan Dennis Reimer, Hussam Amrouch, Sybille Hellebrand, Hans-Joachim Wunderlich

Proceedings of the IEEE International Test Conference, 2024

2023

Robust Pattern Generation for Small Delay Faults Under Process Variations.

Hanieh Jafarzadeh, Florian Klemme, Jan Dennis Reimer, Zahra Paria Najafi-Haghi, Hussam Amrouch, Sybille Hellebrand, Hans-Joachim Wunderlich

Proceedings of the IEEE International Test Conference, 2023

Approximate Communication: Balancing Performance, Power, Reliability, and Safety.

Abdalrhman Badran, Somayeh Sadeghi Kohan, Jan Dennis Reimer, Sybille Hellebrand

Proceedings of the IEEE European Test Symposium, 2023

Optimizing the Streaming of Sensor Data with Approximate Communication.

Somayeh Sadeghi Kohan, Jan Dennis Reimer, Sybille Hellebrand, Hans-Joachim Wunderlich

Proceedings of the 32nd IEEE Asian Test Symposium, 2023

2020

Logic Fault Diagnosis of Hidden Delay Defects.

Stefan Holst, Matthias Kampmann, Alexander Sprenger, Jan Dennis Reimer, Sybille Hellebrand, Hans-Joachim Wunderlich, Xiaoqing Wen

Proceedings of the IEEE International Test Conference, 2020

Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study.

Alexander Sprenger, Somayeh Sadeghi Kohan, Jan Dennis Reimer, Sybille Hellebrand

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020