Alice C. Parker

According to our database1, Alice C. Parker authored at least 103 papers between 1976 and 2019.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 1991, "For contributions to design automation in the areas of high-level synthesis, hardware descriptive languages, and design representation.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Homepage:

On csauthors.net:

Bibliography

2019
Simulation Studies of Neuronal Modulation Using Magneto-electric Nanoparticles for Astrocyte Stimulation.
Proceedings of the 2019 9th International IEEE/EMBS Conference on Neural Engineering (NER), 2019

An Electronic Neuron with Input-Specific Spiking.
Proceedings of the International Joint Conference on Neural Networks, 2019

Analog Neurons that Signal with Spiking Frequencies.
Proceedings of the International Conference on Neuromorphic Systems, 2019

Analog Neurons with Dopamine-Modulated STDP.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

2017
A switched-capacitor dendritic arbor for low-power neuromorphic applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Noisy neuromorphic neurons with RPG on-chip noise source.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

A power-efficient biomimetic intra-branch dendritic adder.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

C. elegans neuromorphic neural network exhibiting undulating locomotion.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

2016
Noisy neuromorphic circuit modeling Obsessive Compulsive Disorder.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Neuromorphic circuit modeling directional selectivity in the visual cortex.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016

A neuromorphic circuit mimicking biological short-term memory.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016

A CMOS circuit implementation of retrograde signaling in astrocyte-neuron networks.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

2015
An Astrocyte Neuromorphic Circuit That Influences Neuronal Phase Synchrony.
IEEE Trans. Biomed. Circuits and Systems, 2015

Neural circuits for touch-induced locomotion in Caenorhabditis elegans.
Proceedings of the 2015 International Joint Conference on Neural Networks, 2015

A hybrid neuromorphic circuit demonstrating schizophrenic symptoms.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

2014
An adaptable CMOS depressing synapse with detection of changes in input spike rate.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Astrocyte on neuronal phase synchrony in CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A biomimetic nanoelectronic neuron with enhanced spike timing.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Border ownership in a nano-neuromorphic circuit using nonlinear dendritic computations.
Proceedings of the 2014 International Joint Conference on Neural Networks, 2014

Dynamic spike threshold and nonlinear dendritic computation for coincidence detection in neuromorphic circuits.
Proceedings of the 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014

2013
Synaptic Variability in a Cortical Neuromorphic Circuit.
IEEE Trans. Neural Netw. Learning Syst., 2013

A CMOS neuromorphic approach to emulate neuro-astrocyte interactions.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013

2011
An in-silico glial microdomain to invoke excitability in cortical neural networks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A directionally-selective neuromorphic circuit based on reciprocal synapses in Starburst Amacrine Cells.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

2007
3D Tree-Structured Object Tracking for Autonomous Ground Vehicles.
Proceedings of the Fourth Canadian Conference on Computer and Robot Vision (CRV 2007), 2007

2006
Exploring network topology evolution through evolutionary computations.
Proceedings of the Genetic and Evolutionary Computation Conference, 2006

Towards a Nanoscale Artificial Cortex.
Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, 2006

2004
Interconnect-based system-level energy and power prediction to guide architecture exploration.
IEEE Trans. VLSI Syst., 2004

Synthesizing complex multimedia network topologies using an evolutionary approach.
Proceedings of the IEEE Congress on Evolutionary Computation, 2004

2003
i-CAD: A Rapid Prototyping CAD Tool for Intranet Design.
Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP 2003), 2003

2002
Automated design of hierarchical intranets.
Comput. Commun., 2002

2000
Computer-aided system integration for data-intensive multimedia applications (poster session).
Proceedings of the 8th ACM International Conference on Multimedia 2000, Los Angeles, CA, USA, October 30, 2000

1999
System-Level Design.
Proceedings of the VLSI Handbook., 1999

1998
Freedom: Statistical Behavioral Estimation of System Energy and Power.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

An Evolutionary Approach to System Redesign.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Accuracy sensitive word-length selection for algorithm optimization.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1997
Rapid Synthesis of Multi-Chip Systems.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Incorporating Imprecise Computation into System-Level Design of Application-Specific Heterogeneous Multiprocessors.
Proceedings of the 34st Conference on Design Automation, 1997

1995
A methodology and design tools to support system-level VLSI design.
IEEE Trans. VLSI Syst., 1995

Optimal ILP-Based Approach for Throughput Optimization Using Simultaneous Algorithm/Architecture Matching and Retiming.
Proceedings of the 32st Conference on Design Automation, 1995

1994
Synthesis of application-specific multiprocessor systems including memory components.
VLSI Signal Processing, 1994

SMASH: a program for scheduling memory-intensive application-specific hardware.
Proceedings of the 7th International Symposium on High Level Synthesis, 1994

A hybrid numeric/symbolic program for checking functional and timing compatibility of synthesized designs.
Proceedings of the 7th International Symposium on High Level Synthesis, 1994

Experience with Image Compression Chip Design using Unified System Construction Tools.
Proceedings of the 31st Conference on Design Automation, 1994

Optimal synthesis of application specific heterogeneous pipelined multiprocessors.
Proceedings of the International Conference on Application Specific Array Processors, 1994

1993
High Performance Embedded System Optimization Using Algebraic and Generalized Retiming Techniques.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Critical Path Minimization Using Retiming and Algebraic Speed-Up.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
Predicting system-level area and delay for pipelined and nonpipelined designs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1992

SOS: Synthesis of application-specific heterogeneous multiprocessor systems.
J. Parallel Distributed Comput., 1992

Synthesis of application-specific heterogeneous multiprocessor systems.
Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, 1992

High-Level Synthesis with Pin Constraints for Multiple-Chip Designs.
Proceedings of the 29th Design Automation Conference, 1992

1991
The ADAM design planning engine.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1991

3D Scheduling: High-Level Synthesis with Floorplanning.
Proceedings of the 28th Design Automation Conference, 1991

Synthesis of Application-Specific Multiprocessor Architectures.
Proceedings of the 28th Design Automation Conference, 1991

The Effects of Physical Design Characteristics on the Area-Performance Tradeoff Curve.
Proceedings of the 28th Design Automation Conference, 1991

CHOP: A Constraint-Driven System-Level Partitioner.
Proceedings of the 28th Design Automation Conference, 1991

1990
Data Path Tradeoffs Using MABAL.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989
Techniques for area estimation of VLSI layouts.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1989

The EVE VLSI information management environment.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

Experience with ADAM Synthesis System.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988
Sehwa: a software package for synthesis of pipelines from behavioral specifications.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1988

Theory of Clocking for Maximum Execution Overlap of High-Speed Digital Systems.
IEEE Trans. Computers, 1988

Area-time model for synthesis of non-pipelined designs.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

Tutorial on High-Level Synthesis.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

Module Selection for Pipelined Synthesis.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987
Understanding System Specifications Written in Natural Language.
Proceedings of the 10th International Joint Conference on Artificial Intelligence. Milan, 1987

REAL: a program for REgister ALlocation.
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

Predicting Area-Time Tradeoffs for Pipelined Design.
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

PHRAN-SPAN: A Natural Language Interface for System Specifications.
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

Phrasal Analysis of Long Noun Sequences.
Proceedings of the 25th Annual Meeting of the Association for Computational Linguistics, 1987

1986
Stochastic Models for Wireability Analysis of Gate Arrays.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1986

MAHA: a program for datapath synthesis.
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

Sehwa: a program for synthesis of pipelines.
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

PLEST: a program for area estimation of VLSI integrated circuits.
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

A design utility manager: the ADAM planning engine.
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

1985
An Extensible Object-Oriented Approach to Databases for VLSI/CAD.
Proceedings of the VLDB'85, 1985

Synthesis of optimal clocking schemes.
Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985

The ADAM advanced design automation system: overview, planner and natural language interface.
Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985

1984
A Representation for Shape Based on Peaks and Ridges in the Difference of Low-Pass Transform.
IEEE Trans. Pattern Anal. Mach. Intell., 1984

On the relation between wire length distributions and placement of logic on master slice ICs.
Proceedings of the 21st Design Automation Conference, 1984

A general methodology for synthesis and verification of register-transfer designs.
Proceedings of the 21st Design Automation Conference, 1984

1983
A Formal Method for the Specification, Analysis, and Design of Register-Transfer Level Digital Logic.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1983

An Abstract Model of Behavior for Hardware Descriptions.
IEEE Trans. Computers, 1983

The effect of register-transfer design tradeoffs on chip area and performance.
Proceedings of the 20th Design Automation Conference, 1983

1982
Synthesis of Hardware for the Control of Digital Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1982

Automated Synthesis of Digital Hardware.
IEEE Trans. Computers, 1982

1981
SLIDE: An I/O Hardware Descriptive Language.
IEEE Trans. Computers, 1981

Algorithms for multiple-criterion design of microprogrammed control hardware.
Proceedings of the 18th Design Automation Conference, 1981

Digital system simulation: Current status and future trends or darwin's theory of simulation.
Proceedings of the 18th Design Automation Conference, 1981

Microprogramming: the challenges of VLSI.
Proceedings of the American Federation of Information Processing Societies: 1981 National Computer Conference, 1981

1980
The Automated Dictionary.
IEEE Computer, 1980

The SLIDE simulator: A facility for the design and analysis of computer interconnections.
Proceedings of the 17th Design Automation Conference, 1980

1979
Bus System for the Military Computer Family.
IEEE Computer, 1979

The CMU design automation system: An example of automated data path design.
Proceedings of the 16th Design Automation Conference, 1979

1978
The Application of a Hardware Descriptive Language for Design Automation.
Proceedings of the Information Technology '78: Proceedings of the 3rd Jerusalem Conference on Information Technology (JCIT3), 1978

Description and Simulation of Microcode Execution.
Proceedings of the 5th Annual Symposium on Computer Architecture, 1978

Register-transfer level digital design automation: The allocation process.
Proceedings of the 15th Design Automation Conference, 1978

1977
Hardware/Software Tradeoffs in A Variable Word Width, Variable Queue Length Buffer Memory.
Proceedings of the 4th Annual Symposium on Computer Architecture, 1977

The Design and Implementation of a Real-Time Sound Generation System.
Proceedings of the 4th Annual Symposium on Computer Architecture, 1977

The Carnegie-Mellon Computer Music System Digital Hardware.
Proceedings of the 1977 International Computer Music Conference, 1977

Envelope Control with an Optical Keyboard.
Proceedings of the 1977 International Computer Music Conference, 1977

1976
The Design of a User-Programmable Digital Interface.
Proceedings of the 3rd Annual Symposium on Computer Architecture, 1976

An Input Interface for Real-Time Digital Sound Generation System.
Proceedings of the 3rd Annual Symposium on Computer Architecture, 1976


  Loading...