Sarma Sastry

According to our database1, Sarma Sastry authored at least 19 papers between 1984 and 1993.

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Bibliography

1993
Probabilistic characterization of controllability in general homogeneous circuits.
Comput. Aided Des., 1993

Statistical Analysis of Controllability.
Proceedings of the Sixth International Conference on VLSI Design, 1993

1992
Boolean Matching Using Binary Decision Diagrams with Applications to Logic Synthesis and Verification.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

On the Distribution of Fault Coverage and Test length in Random Testing of Combinational Circuits.
Proceedings of the 29th Design Automation Conference, 1992

Edge-Valued Binary Decision Diagrams for Multi-Level Hierarchical Verification.
Proceedings of the 29th Design Automation Conference, 1992

1991
Estimating the minimum of partitioning and floorplanning problems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Test efficiency analysis of random self-test of sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

VYUHA: A detailed router for multiple routing models.
Integr., 1991

Topological via minimization and routing.
Proceedings of the First Great Lakes Symposium on VLSI, 1991

A Branching Process Model for Observability Analysis of Combinational Circuits.
Proceedings of the 28th Design Automation Conference, 1991

Flexible Transistor Matrix (FTM).
Proceedings of the 28th Design Automation Conference, 1991

1989
A hardware accelerator for hierarchical VLSI routing.
Integr., 1989

Parallel Placement on Hypercube Architecture.
Proceedings of the International Conference on Parallel Processing, 1989

An Investigation into Statistical Properties of Partitioning and Floorplanning Problems.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988
Detectability of CMOS stuck-open faults using random and pseudorandom test sequences.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

Parallel Placement on Reduced Array Architecture.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987
A General Purpose VLSI Array for Efficient Signal and Image Processsing.
Proceedings of the International Conference on Parallel Processing, 1987

1986
Stochastic Models for Wireability Analysis of Gate Arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986

1984
On the relation between wire length distributions and placement of logic on master slice ICs.
Proceedings of the 21st Design Automation Conference, 1984


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