Amrutha Iyer
According to our database1,
Amrutha Iyer
authored at least 2 papers
between 2016 and 2017.
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Bibliography
2017
A 0.5-9.5-GHz, 1.2-µs Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling.
IEEE J. Solid State Circuits, 2017
2016
19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ±1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016