Amrutha Iyer

According to our database, Amrutha Iyer authored at least 4 papers between 2016 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2024

7.1 A 2.69pJ/b 212Gb/s DSP-Based PAM-4 Transceiver for Optical Direct-Detect Application in 5nm FinFET.

J. Q. Wang, Amber Tan, Amrutha Iyer, A. Fan, A. Farhoodfar, B. Alnabulsi, B. Smith, Chang-Feng Loi, Cheng-Ru Ho, D. Cartina, Jamal Riani, J. Casanova, Karthik Raviprakash, L. Patra, Luke Wang, M. Bachu, Sagar Ray, Sau Siong Chong, S. Dallaire, The Linh Nguyen, Tzu-Fan Wu, Vishal Giridharan, V. Gurumoorthy, X. Ding, Y. Yin, Zhuochao Sun, Steve Jantzi, Lawrence Tse

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023

A 200Gb/s Low Power DSP-Based Optical Receiver and Transmitter with Integrated TIA and Laser Drivers.

Arik Zafrany, Daniel Burgos, Li Cai, Sau Siong Chong, Colin Cramm, Sadegh Dadash, Vishal Giridharan, Vivek Gurumoorthy, Belal Helal, Cheng-Ru Ho, Amrutha Iyer, Steve Jantzi, Chang-Feng Loi, The Linh Nguyen, Kevin Parker, Ed Pillai, Karthik Raviprakash, Sagar Ray, Paolo Rossi, Zhuochao Sun, Amber Tan, Lawrence Tse, Brian Wall, Luke Wang, Jeffrey Wang, Tzu-Fan Wu

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2023

2017

A 0.5-9.5-GHz, 1.2-µs Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling.

Fazil Ahmad, Greg Unruh, Amrutha Iyer, Pin-En Su, Sherif Abdalla, Bo Shen, Mark Chambers, Ichiro Fujimori

IEEE J. Solid State Circuits, 2017

2016

19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ±1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC.

Fazil Ahmad, Greg Unruh, Amrutha Iyer, Pin-En Su, Sherif Abdalla, Bo Shen, Mark Chambers, Ichiro Fujimori

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016