Greg Unruh

According to our database, Greg Unruh authored at least 12 papers between 2011 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2018

A 16b 6GS/S nyquist DAC with IMD <-90dBc up to 1.9GHz in 16nm CMOS.

Chi-Hung Lin, Jackie Koon Lun Wong, Tae-Youn Kim, Guangxi Ray Xie, Donald Major, Greg Unruh, Sunny Raj Dommaraju, Hans Eberhart, Ardie G. Venes

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017

A 0.5-9.5-GHz, 1.2-µs Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling.

Fazil Ahmad, Greg Unruh, Amrutha Iyer, Pin-En Su, Sherif Abdalla, Bo Shen, Mark Chambers, Ichiro Fujimori

IEEE J. Solid State Circuits, 2017

2016

A 2.7 mW/Channel 48-1000 MHz Direct Sampling Full-Band Cable Receiver.

Jiangfeng Wu, Giuseppe Cusmai, Acer Wei-Te Chou, Tao Wang, Bo Shen, Vijayaramalingam Periasamy, Ming-Hung Hsieh, Chun-Ying Chen, Lin He, Loke Kun Tan, Aravind Padyana, Vincent Cheng-Hsun Yang, Gregory Unruh, Jackie Koon Lun Wong, Bryan Juo-Jung Hung, Massimo Brandolini, Maco Sha-Ting Lin, Xi Chen, Yen Ding, Yen-Jen Ko, Young J. Shin, Ada Hing T. Hung, Binning Chen, Cynthia Dang, Deepak Lakshminarasimhan, Iris Hong Liu, Jerry Lin, Kowen Lai, Larry Wassermann, Ayaskant Shrivastava, Chi-Ming Hsiao, Chun-Sheng Huang, Jianlong Chen, Lakshminarasimhan Krishnan, Ning-Yi Wang, Pin-En Su, Tianwei Li, Wei-Ta Shih, Yau-Cheng Yang, Peter Cangiane, Randall Perlow, William Ngai, Hanson Hung-Sen Huang, James Y. C. Chang, Xicheng Jiang, Ardie G. Venes, Ramon Ray Gomez

IEEE J. Solid State Circuits, 2016

A 180 mW multistandard TV tuner in 28 nm CMOS.

Jianhong Xiao, Weinan Gao, Xiaojing Xu, Dave S.-H. Chang, Jiang Cao, Runhua Sun, Vijay Periasamy, Ning-Yi Wang, Xi Chen, Greg Unruh, Takayuki Hayashi, Tai-Hong Chih, Lakshminarasimhan Krishnan, Kuo-Ken Huang, Sunny Raj Dommaraju, Guowen Wei, Bo Shen, Ardie G. Venes, Dongsoo Koh, James Y. C. Chang

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

27.6 A 4GS/s 13b pipelined ADC with capacitor and amplifier sharing in 16nm CMOS.

Jiangfeng Wu, Acer Wei-Te Chou, Tianwei Li, Rong Wu, Tao Wang, Giuseppe Cusmai, Sha-Ting Lin, Cheng-Hsun Yang, Greg Unruh, Sunny Raj Dommaraju, Mo M. Zhang, Po Tang Yang, Wei-Ting Lin, Xi Chen, Dongsoo Koh, Qingqi Dou, Hemasundar Mohan Geddada, Juo-Jung Hung, Massimo Brandolini, Young Shin, Hung Sen Huang, Chun-Ying Chen, Ardie G. Venes

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ±1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoC.

Fazil Ahmad, Greg Unruh, Amrutha Iyer, Pin-En Su, Sherif Abdalla, Bo Shen, Mark Chambers, Ichiro Fujimori

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

A 2.7 GHz to 7 GHz Fractional-N LC-PLL Utilizing Multi-Metal Layer SoC Technology in 28 nm CMOS.

Chang-Hyeon Lee, Lindel Kabalican, Yan Ge, Hendra Kwantono, Greg Unruh, Mark Chambers, Ichiro Fujimori

IEEE J. Solid State Circuits, 2015

A 5 GS/s 150 mW 10 b SHA-Less Pipelined/SAR Hybrid ADC for Direct-Sampling Systems in 28 nm CMOS.

Massimo Brandolini, Young Shin, Karthik Raviprakash, Tao Wang, Rong Wu, Hemasundar Mohan Geddada, Yen-Jen Ko, Yen Ding, Chun-Sheng Huang, Wei-Ta Shih, Ming-Hung Hsieh, Wei-Te Chou, Tianwei Li, Ayaskant Shrivastava, Yi-Chun Chen, Bryan Juo-Jung Hung, Giuseppe Cusmai, Jiangfeng Wu, Mo M. Zhang, Yuan Yao, Greg Unruh, Ardie G. Venes, Hung Sen Huang, Chun-Ying Chen

IEEE J. Solid State Circuits, 2015

A 2.7mW/Channel 48-to-1000MHz Direct Sampling Full-Band Cable Receiver.

Jiangfeng Wu, Giuseppe Cusmai, Acer Wei-Te Chou, Tao Wang, Bo Shen, Vijayaramalingam Periasamy, Ming-Hung Hsieh, Chun-Ying Chen, Lin He, Loke Tan, Aravind Padyana, Cheng-Hsun Yang, Gregory Unruh, Jackie Koon Lun Wong, Juo-Jung Hung, Massimo Brandolini, Sha-Ting Lin, Xi Chen, Yen Ding, Yen-Jen Ko, Young Shin, Ada Hing T. Hung, Binning Chen, Cynthia Dang, Deepak Lakshminarasimhan, Iris Hong Liu, Jerry Lin, Kowen Lai, Larry Wassermann, Ayaskant Shrivastava, Chi-Ming Hsiao, Chun-Sheng Huang, Jianlong Chen, Lakshminarasimhan Krishnan, Ning-Yi Wang, Pin-En Su, Tianwei Li, Wei-Ta Shih, Yau-Cheng Yang, Peter Cangiane, Randall Perlow, William Ngai, Hung Sen Huang, James Y. C. Chang, Xicheng Jiang, Ardie G. Venes, Ramon Gomez

Proceedings of the Symposium on VLSI Circuits, 2015

26.6 A 5GS/S 150mW 10b SHA-less pipelined/SAR hybrid ADC in 28nm CMOS.

Massimo Brandolini, Young Shin, Karthik Raviprakash, Tao Wang, Rong Wu, Hemasundar Mohan Geddada, Yen-Jen Ko, Yen Ding, Chun-Sheng Huang, Wei-Ta Shih, Ming-Hung Hsieh, Wei-Te Chou, Tianwei Li, Ayaskant Shrivastava, Yi-Chun Chen, Juo-Jung Hung, Giuseppe Cusmai, Jiangfeng Wu, Mo M. Zhang, Greg Unruh, Ardie G. Venes, Hung Sen Huang, Chun-Ying Chen

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014

A 2.7GHz to 7GHz fractional-N LCPLL utilizing multimetal layer SoC technology in 28nm CMOS.

Chang-Hyeon Lee, Lindel Kabalican, Yan Ge, Hendra Kwantono, Greg Unruh, Mark Chambers, Ichiro Fujimori

Proceedings of the Symposium on VLSI Circuits, 2014

2011

A 19 mW/lane Serdes transceiver for SFI-5.1 application.

Siavash Fallahi, Delong Cui, Deyi Pi, Rose Zhu, Greg Unruh, Marcel Lugthart, Afshin Momtaz

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011