Anand Ramalingam

According to our database, Anand Ramalingam authored at least 8 papers between 2005 and 2008.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2008

Latch Modeling for Statistical Timing Analysis.

Sean X. Shi, Anand Ramalingam, Daifeng Wang, David Z. Pan

Proceedings of the Design, Automation and Test in Europe, 2008

2007

Wakeup Scheduling in MTCMOS Circuits Using Successive Relaxation to Minimize Ground Bounce.

Anand Ramalingam, Anirudh Devgan, David Z. Pan

J. Low Power Electron., 2007

Accurate power grid analysis with behavioral transistor network modeling.

Anand Ramalingam, Giri Devarayanadurg, David Z. Pan

Proceedings of the 2007 International Symposium on Physical Design, 2007

Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis.

Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Michael Orshansky, David Z. Pan

Proceedings of the 44th Design Automation Conference, 2007

2006

Accurate Thermal Analysis Considering Nonlinear Thermal Conductivity.

Anand Ramalingam, David Z. Pan, Frank Liu, Sani R. Nassif

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

An accurate sparse matrix based framework for statistical static timing analysis.

Anand Ramalingam, Gi-Joon Nam, Ashish Kumar Singh, Michael Orshansky, Sani R. Nassif, David Z. Pan

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Robust analytical gate delay modeling for low voltage circuits.

Anand Ramalingam, Sreekumar V. Kodakara, Anirudh Devgan, David Z. Pan

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Sleep transistor sizing using timing criticality and temporal currents.

Anand Ramalingam, Bin Zhang, Anirudh Devgan, David Z. Pan

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005