Andhi Janapsatya

According to our database, Andhi Janapsatya authored at least 13 papers between 2004 and 2010.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2010

Rapid runtime estimation methods for pipelined MPSoCs.

Haris Javaid, Andhi Janapsatya, Mohammad Shihabul Haque, Sri Parameswaran

Proceedings of the Design, Automation and Test in Europe, 2010

Dueling CLOCK: Adaptive cache replacement policy based on the CLOCK algorithm.

Andhi Janapsatya, Aleksandar Ignjatovic, Jorgen Peddersen, Sri Parameswaran

Proceedings of the Design, Automation and Test in Europe, 2010

DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy.

Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran

Proceedings of the Design, Automation and Test in Europe, 2010

SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy.

Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran

Proceedings of the 47th Design Automation Conference, 2010

2009

SuSeSim: a fast simulation strategy to find optimal L1 cache configuration for embedded systems.

Mohammad Shihabul Haque, Andhi Janapsatya, Sri Parameswaran

Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

HitME: low power Hit MEmory buffer for embedded systems.

Andhi Janapsatya, Sri Parameswaran, Aleksandar Ignjatovic

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2007

Instruction trace compression for rapid instruction cache simulation.

Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran, Jörg Henkel

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Exploiting statistical information for implementation of instruction scratchpad memory in embedded system.

Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran

IEEE Trans. Very Large Scale Integr. Syst., 2006

Finding optimal L1 cache configuration for embedded systems.

Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

A novel instruction scratchpad memory optimization method based on concomitance metric.

Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Optimization of instruction memory for embedded systems.

Andhi Janapsatya

PhD thesis, 2005

Rapid Embedded Hardware/Software System Generation.

Jorgen Peddersen, Seng Lin Shee, Andhi Janapsatya, Sri Parameswaran

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

2004

Hardware/software managed scratchpad memory for embedded system.

Andhi Janapsatya, Sri Parameswaran, Aleksandar Ignjatovic

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004