Mohammad Shihabul Haque

According to our database, Mohammad Shihabul Haque authored at least 11 papers between 2009 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2018

Predictability and Performance Aware Replacement Policy PVISAM for Unified Shared Caches in Real-time Multicores.

Mohammad Shihabul Haque, Arvind Easwaran

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Contract-Based Hierarchical Resilience Management for Cyber-Physical Systems.

Mohammad Shihabul Haque, Daniel Jun Xian Ng, Arvind Easwaran, Karthikeyan Thangamariappan

Computer, 2018

A Self-Reconfiguring Cache Architecture to Improve Control Quality in Cyber-Physical Systems.

Mohammad Shihabul Haque, Sriram Vasudevan, Alamuri Sriram Nihar, Arvind Easwaran, Akash Kumar, Y. C. Tay

Proceedings of the 21st IEEE International Symposium on Real-Time Distributed Computing, 2018

2015

Accelerating non-volatile/hybrid processor cache design space exploration for application specific embedded systems.

Mohammad Shihabul Haque, Ang Li, Akash Kumar, Qingsong Wei

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2013

TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs.

Mohammad Shihabul Haque, Akash Kumar, Yajun Ha, Qiang Wu, Shaobo Luo

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

DIMSim: a rapid two-level cache simulation approach for deadline-based MPSoCs.

Mohammad Shihabul Haque, Roshan G. Ragel, Jude Angelo Ambrose, Swarnalatha Radhakrishnan, Sri Parameswaran

Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011

CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation technique.

Mohammad Shihabul Haque, Jorgen Peddersen, Sri Parameswaran

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010

Rapid runtime estimation methods for pipelined MPSoCs.

Haris Javaid, Andhi Janapsatya, Mohammad Shihabul Haque, Sri Parameswaran

Proceedings of the Design, Automation and Test in Europe, 2010

DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy.

Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran

Proceedings of the Design, Automation and Test in Europe, 2010

SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy.

Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran

Proceedings of the 47th Design Automation Conference, 2010

2009

SuSeSim: a fast simulation strategy to find optimal L1 cache configuration for embedded systems.

Mohammad Shihabul Haque, Andhi Janapsatya, Sri Parameswaran

Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009