Jörg Henkel

According to our database1, Jörg Henkel authored at least 416 papers between 1993 and 2019.

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Bibliography

2019
Dynamic Guardband Selection: Thermal-Aware Optimization for Unreliable Multi-Core Systems.
IEEE Trans. Computers, 2019

2018
Preemption of the Partial Reconfiguration Process to Enable Real-Time Computing With FPGAs.
TRETS, 2018

Guest Editorial for the Special Issue of ESWEEK 2016.
ACM Trans. Embedded Comput. Syst., 2018

Distributed Trade-Based Edge Device Management in Multi-Gateway IoT.
TCPS, 2018

Reliability in Super- and Near-Threshold Computing: A Unified Model of RTN, BTI, and PV.
IEEE Trans. on Circuits and Systems, 2018

Co-Scheduling on Fused CPU-GPU Architectures With Shared Last Level Caches.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

SlackHammer: Logic Synthesis for Graceful Errors Under Frequency Scaling.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Aging-Aware Boosting.
IEEE Trans. Computers, 2018

Recent advances in EM and BTI induced reliability modeling, analysis and optimization (invited).
Integration, 2018

Guest Editors' Introduction.
Embedded Systems Letters, 2018

Managing Electric Vehicles.
IEEE Design & Test, 2018

Self-Awareness in Systems on Chip, Part II.
IEEE Design & Test, 2018

Time-Critical Systems Design, Part II.
IEEE Design & Test, 2018

Test for Automotive.
IEEE Design & Test, 2018

From the EIC: Time-Critical Systems Design.
IEEE Design & Test, 2018

Design and Test of Energy-Efficient, High-Performance, and Secure Computing Technologies via Accelerators.
IEEE Design & Test, 2018

Negative Capacitance Transistor to Address the Fundamental Limitations in Technology Scaling: Processor Performance.
IEEE Access, 2018

Voltage Adaptation Under Temperature Variation.
Proceedings of the 15th International Conference on Synthesis, 2018

Scalable Dynamic Task Scheduling on Adaptive Many-Core.
Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018

Pareto-Optimal Power- and Cache-Aware Task Mapping for Many-Cores with Distributed Shared Last-Level Cache.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

Weighted time lag plot defect parameter extraction and GPU-based BTI modeling for BTI variability.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

Reliability Estimations of Large Circuits in Massively-Parallel GPU-SPICE.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Trading Off Temperature Guardbands via Adaptive Approximations.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

Dynamic resource management for heterogeneous many-cores.
Proceedings of the International Conference on Computer-Aided Design, 2018

Estimating and optimizing BTI aging effects: from physics to CAD.
Proceedings of the International Conference on Computer-Aided Design, 2018

Highly efficient and accurate seizure prediction on constrained IoT devices.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Task scheduling for many-cores with S-NUCA caches.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Compiler-driven error analysis for designing approximate accelerators.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

QoS-aware stochastic power management for many-cores.
Proceedings of the 55th Annual Design Automation Conference, 2018

Aging-constrained performance optimization for multi cores.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Efficient Partial Online Synthesis of Special Instructions for Reconfigurable Processors.
IEEE Trans. VLSI Syst., 2017

Timing Analysis of Tasks on Runtime Reconfigurable Processors.
IEEE Trans. VLSI Syst., 2017

Energy Efficiency for Clustered Heterogeneous Multicores.
IEEE Trans. Parallel Distrib. Syst., 2017

Optimal Greedy Algorithm for Many-Core Scheduling.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Aging Resilience and Fault Tolerance in Runtime Reconfigurable Architectures.
IEEE Trans. Computers, 2017

Application-Guided Power-Efficient Fault Tolerance for H.264 Context Adaptive Variable Length Coding.
IEEE Trans. Computers, 2017

Thermal Safe Power (TSP): Efficient Power Budgeting for Heterogeneous Manycore Systems in Dark Silicon.
IEEE Trans. Computers, 2017

Probabilistic Error Modeling for Approximate Adders.
IEEE Trans. Computers, 2017

Fine-Grained Checkpoint Recovery for Application-Specific Instruction-Set Processors.
IEEE Trans. Computers, 2017

Power Density-Aware Resource Management for Heterogeneous Tiled Multicores.
IEEE Trans. Computers, 2017

Defragmentation of Tasks in Many-Core Architecture.
TACO, 2017

FAMe-TM: Formal analysis methodology for task migration algorithms in Many-Core systems.
Sci. Comput. Program., 2017

Complexity control of HEVC encoders targeting real-time constraints.
J. Real-Time Image Processing, 2017

Theorem proving based Formal Verification of Distributed Dynamic Thermal Management schemes.
J. Parallel Distrib. Comput., 2017

CoRQ: Enabling Runtime Reconfiguration Under WCET Guarantees for Real-Time Systems.
Embedded Systems Letters, 2017

Report of the 2016 Embedded Systems Week (ESWEEK).
IEEE Design & Test, 2017

Self-Aware On-Chip Systems.
IEEE Design & Test, 2017

Verification and Test.
IEEE Design & Test, 2017

Cyber-Physical Systems Security and Privacy.
IEEE Design & Test, 2017

Emerging Memory Technologies.
IEEE Design & Test, 2017

Power Density.
IEEE Design & Test, 2017

3D Test.
IEEE Design & Test, 2017

Interdependencies of Degradation Effects and Their Impact on Computing.
IEEE Design & Test, 2017

Computer Engineers' Challenges for the Next Decade: The Triangle of Power Density, Circuit Degradation, and Reliability.
IEEE Computer, 2017

The triangle of power density, circuit degradation and reliability.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

The triangle of power density, circuit degradation and reliability.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Auto-SI: An adaptive reconfigurable processor with run-time loop detection and acceleration.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Containing Guardbands: From the Macro to Micro Time Domain.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2017

Shallow Water Waves on a Deep Technology Stack: Accelerating a Finite Volume Tsunami Model Using Reconfigurable Hardware in Invasive Computing.
Proceedings of the Euro-Par 2017: Parallel Processing Workshops, 2017

Evaluating and mitigating degradation effects in multimedia circuits.
Proceedings of the 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia, 2017

Hardware and software innovations in energy-efficient system-reliability monitoring.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

Scalable probabilistic power budgeting for many-cores.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Ultra-low power and dependability for IoT devices (Invited paper for IoT technologies).
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

CAnDy-TM: Comparative analysis of dynamic thermal management in many-cores using model checking.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Optimizing temperature guardbands.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Soft error-aware architectural exploration for designing reliability adaptive cache hierarchies in multi-cores.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Towards Aging-Induced Approximations.
Proceedings of the 54th Annual Design Automation Conference, 2017

Emerging (un-)reliability based security threats and mitigations for embedded systems: special session.
Proceedings of the 2017 International Conference on Compilers, 2017

Containing guardbands.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Analysis and Mapping for Thermal and Energy Efficiency of 3-D Video Processing on 3-D Multicore Processors.
IEEE Trans. VLSI Syst., 2016

Two-State Checkpointing for Energy-Efficient Fault Tolerance in Hard Real-Time Systems.
IEEE Trans. VLSI Syst., 2016

Power-Efficient Workload Balancing for Video Applications.
IEEE Trans. VLSI Syst., 2016

SPMPool: Runtime SPM Management for Memory-Intensive Applications in Embedded Many-Cores.
ACM Trans. Embedded Comput. Syst., 2016

Reliability-Aware Adaptations for Shared Last-Level Caches in Multi-Cores.
ACM Trans. Embedded Comput. Syst., 2016

Resource and Throughput Aware Execution Trace Analysis for Efficient Run-Time Mapping on MPSoCs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Architecting On-Chip DRAM Cache for Simultaneous Miss Rate and Latency Reduction.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Content-Aware Low-Power Configurable Aging Mitigation for SRAM Memories.
IEEE Trans. Computers, 2016

Scalable Power Management for On-Chip Systems with Malleable Applications.
IEEE Trans. Computers, 2016

Cross-Layer Software Dependability on Unreliable Hardware.
IEEE Trans. Computers, 2016

Task Mapping for Redundant Multithreading in Multi-Cores with Reliability and Performance Heterogeneity.
IEEE Trans. Computers, 2016

Extending the WCET Problem to Optimize for Runtime-Reconfigurable Processors.
TACO, 2016

Invasive computing for timing-predictable stream processing on MPSoCs.
it - Information Technology, 2016

Dark silicon management: an integrated and coordinated cross-layer approach.
it - Information Technology, 2016

Variability and Reliability Awareness in the Age of Dark Silicon.
IEEE Design & Test, 2016

Best in Test.
IEEE Design & Test, 2016

New Directions in Analog/Mixed-Signal Design and Test.
IEEE Design & Test, 2016

Designing and Testing Implantable Medical Devices.
IEEE Design & Test, 2016

Robustness for 3-D Circuits - Industrial Perspectives.
IEEE Design & Test, 2016

Three-Dimensional Integrated Circuits.
IEEE Design & Test, 2016

Approximate Computing: Solving Computing's Inefficiency Problem?
IEEE Design & Test, 2016

Computation offloading and resource allocation for low-power IoT edge devices.
Proceedings of the 3rd IEEE World Forum on Internet of Things, 2016

Cross-Layer Reliability Modeling and Optimization: Compiler and Run-Time System Interactions.
Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, 2016

An Energy-Efficient Middleware for Computation Offloading in Real-Time Embedded Systems.
Proceedings of the 22nd IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2016

Designing reliable, yet energy-efficient guardbands.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Architectural-space exploration of approximate multipliers.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Stress-aware routing to mitigate aging effects in SRAM-based FPGAs.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Aging-aware voltage scaling.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Distributed fair scheduling for many-cores.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Thermal optimization using adaptive approximate computing for video coding.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Power-efficient load-balancing on heterogeneous computing platforms.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Formal probabilistic analysis of distributed resource management schemes in on-chip systems.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Towards performance and reliability-efficient computing in the dark silicon era.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Resource budgeting for reliability in reconfigurable architectures.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Invited - Cross-layer approximate computing: from logic to architectures.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Designing guardbands for instantaneous aging effects.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Improving mobile gaming performance through cooperative CPU-GPU thermal management.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Distributed scheduling for many-cores using cooperative game theory.
Proceedings of the 53rd Annual Design Automation Conference, 2016

An area-efficient consolidated configurable error correction for approximate hardware accelerators.
Proceedings of the 53rd Annual Design Automation Conference, 2016

ageOpt-RMT: compiler-driven variation-aware aging optimization for redundant multithreading.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Reliability-aware design to suppress aging.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Distributed QoS management for internet of things under resource constraints.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

IoT technologies for embedded computing: a survey.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

Power and thermal management in massive multicore chips: theoretical foundation meets architectural innovation and resource allocation.
Proceedings of the 2016 International Conference on Compilers, 2016

Reliable Software for Unreliable Hardware - A Cross Layer Perspective.
Springer, ISBN: 978-3-319-25770-9, 2016

2015
Runtime Resource Allocation for Software Pipelines.
TOPC, 2015

Energy and Peak Power Efficiency Analysis for the Single Voltage Approximation (SVA) Scheme.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Multicast FullHD H.264 Intra Video Encoder Architecture.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

A Reconfigurable Hardware Architecture for Fractional Pixel Interpolation in High Efficiency Video Coding.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Resource-awareness on heterogeneous MPSoCs for image processing.
Journal of Systems Architecture - Embedded Systems Design, 2015

Dependable embedded systems.
it - Information Technology, 2015

Adaptive multi-layer techniques for increased system dependability.
it - Information Technology, 2015

Probabilistic Formal Verification Methodology for Decentralized Thermal Management in On-Chip Systems.
Proceedings of the 24th IEEE International Conference on Enabling Technologies: Infrastructure for Collaborative Enterprises, 2015

Dark Silicon: From Computation to Communication.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

DRVS: Power-efficient reliability management through Dynamic Redundancy and Voltage Scaling under variations.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Power management for mobile games on asymmetric multi-cores.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Hierarchical power budgeting for Dark Silicon chips.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Lucid infrared thermography of thermally-constrained processors.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Energy-efficient multimedia systems for high efficiency video coding.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Connecting the physical and application level towards grasping aging effects.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Reliability degradation in the scope of aging - From physical to system level.
Proceedings of the 10th International Design & Test Symposium, 2015

STRAP: Stress-Aware Placement for Aging Mitigation in Runtime Reconfigurable Architectures.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Mitigating the Power Density and Temperature Problems in the Nano-Era.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Thermal-aware power budgeting for dark silicon chips.
Proceedings of the Sixth International Green and Sustainable Computing Conference, 2015

Floating point acceleration for stream processing applications in dynamically reconfigurable processors.
Proceedings of the 13th IEEE Symposium on Embedded Systems For Real-time Multimedia, 2015

E-pipeline: elastic hardware/software pipelines on a many-core fabric.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Variability-aware dark silicon management in on-chip many-core systems.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Online binding of applications to multiple clock domains in shared FPGA-based systems.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

MatEx: efficient transient and peak temperature computation for compact thermal models.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

ACSEM: accuracy-configurable fast soft error masking analysis in combinatorial circuits.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Adaptive on-the-fly application performance modeling for many cores.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Power-efficient accelerator allocation in adaptive dark silicon many-core systems.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Formal probabilistic analysis of distributed dynamic thermal management.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A deblocking filter hardware architecture for the high efficiency video coding standard.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Malleable NoC: dark silicon inspired adaptable Network-on-Chip.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

EnAAM: energy-efficient anti-aging for on-chip video memories.
Proceedings of the 52nd Annual Design Automation Conference, 2015

A low latency generic accuracy configurable adder.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Thermal constrained resource management for mixed ILP-TLP workloads in dark silicon chips.
Proceedings of the 52nd Annual Design Automation Conference, 2015

New trends in dark silicon.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Hayat: harnessing dark silicon and variability for aging deceleration and balancing.
Proceedings of the 52nd Annual Design Automation Conference, 2015

SuperNet: multimode interconnect architecture for manycore chips.
Proceedings of the 52nd Annual Design Automation Conference, 2015

An approximate compressor for wearable biomedical healthcare monitoring systems.
Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015

dsReliM: Power-constrained reliability management in Dark-Silicon many-core chips under process variations.
Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015

seBoost: Selective boosting for heterogeneous manycores.
Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015

R2Cache: Reliability-aware reconfigurable last-level cache architecture for multi-cores.
Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015

Approximation-aware Multi-Level Cells STT-RAM cache architecture.
Proceedings of the 2015 International Conference on Compilers, 2015

ADAPT: An adaptive manycore methodology for software pipelined applications.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Adaptive Energy Management for Dynamically Reconfigurable Processors.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Reliability-Driven Software Transformations for Unreliable Hardware.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Energy-Efficient Adaptive Pipelined MPSoCs for Multimedia Applications.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

RESI: Register-Embedded Self-Immunity for Reliability Enhancement.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Adaptive embedded computing with i-core.
SIGBED Review, 2014

Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience.
Microelectronics Reliability, 2014

Selected Peer-Reviewed Articles from the 4th European Workshop on CMOS Variability, Karlsruhe, Germany, September 9-11, 2013.
J. Low Power Electronics, 2014

Dark Silicon - A thermal perspective.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

High-speed enoding/decoding technique for reliable data transmission in wireless sensor networks.
Proceedings of the Eleventh Annual IEEE International Conference on Sensing, 2014

Messages from the conference chairs.
Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014

Power- and area-efficient Approximate Wallace Tree Multiplier for error-resilient systems.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Content-driven memory pressure balancing and video memory power management for parallel high efficiency video coding.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

TONE: adaptive temperature optimization for the next generation video encoders.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Peak Power Management for scheduling real-time tasks on heterogeneous many-core systems.
Proceedings of the 20th IEEE International Conference on Parallel and Distributed Systems, 2014

Power efficient and workload balanced tiling for parallelized high efficiency video coding.
Proceedings of the 2014 IEEE International Conference on Image Processing, 2014

Fast hierarchical intra angular mode selection for high efficiency video coding.
Proceedings of the 2014 IEEE International Conference on Image Processing, 2014

Energy-efficient architecture for advanced video memory.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Towards interdependencies of aging mechanisms.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Formal Verification of Distributed Task Migration for Thermal Management in On-Chip Multi-core Systems Using nuXmv.
Proceedings of the Formal Techniques for Safety-Critical Systems, 2014

Run-time accelerator binding for tile-based mixed-grained reconfigurable architectures.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

MORP: makespan optimization for processors with an embedded reconfigurable fabric.
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Dependable task and communication migration in tiled manycore system-on-chip.
Proceedings of the 2014 Forum on Specification and Design Languages, 2014

dSVM: Energy-efficient distributed Scratchpad Video Memory Architecture for the next-generation High Efficiency Video Coding.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Compiler-driven dynamic reliability management for on-chip systems under variabilities.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

hevcDTM: Application-driven Dynamic Thermal Management for High Efficiency Video Coding.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

mDTM: Multi-objective dynamic thermal management for on-chip systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Software architecture of High Efficiency Video Coding for many-core systems with power-efficient workload balancing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

GUARD: GUAranteed Reliability in Dynamically Reconfigurable Systems.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

The EDA Challenges in the Dark Silicon Era: Temperature, Reliability, and Variability Perspectives.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

dTune: Leveraging Reliable Code Generation for Adaptive Dependability Tuning under Process Variation and Aging-Induced Effects.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

ASER: Adaptive Soft Error Resilience for Reliability-Heterogeneous Processors in the Dark Silicon Era.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Multi-Layer Dependability: From Microarchitecture to Application Level.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

CAP: Communication Aware Programming.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

darkNoC: Designing Energy-Efficient Network-on-Chip with Multi-Vt Cells for Dark Silicon.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Dark silicon as a challenge for hardware/software co-design.
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

TSP: Thermal Safe Power - Efficient power budgeting for many-core systems in dark silicon.
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

Hardware/software co-design for a wireless sensor network platform.
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

Automatic custom instruction identification in memory streaming algorithms.
Proceedings of the 2014 International Conference on Compilers, 2014

COREFAB: Concurrent reconfigurable fabric utilization in heterogeneous multi-core systems.
Proceedings of the 2014 International Conference on Compilers, 2014

Low power design of the next-generation High Efficiency Video Coding.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Guest Editorial Special Section on Power-Aware Design for Embedded Systems.
IEEE Trans. Industrial Informatics, 2013

Model Predictive Hierarchical Rate Control With Markov Decision Process for Multiview Video Coding.
IEEE Trans. Circuits Syst. Video Techn., 2013

Test Strategies for Reliable Runtime Reconfigurable Architectures.
IEEE Trans. Computers, 2013

Runtime resource allocation for software pipelines.
Proceedings of the International Workshop on Software and Compilers for Embedded Systems, 2013

Embedded on-chip reliability: it's a thermal challenge.
Proceedings of the International Workshop on Software and Compilers for Embedded Systems, 2013

Reliable code generation and execution on unreliable hardware under joint functional and timing reliability considerations.
Proceedings of the 19th IEEE Real-Time and Embedded Technology and Applications Symposium, 2013

Fast HEVC intra mode decision algorithm based on new evaluation order in the Coding Tree Block.
Proceedings of the 30th Picture Coding Symposium, 2013

Module diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures.
Proceedings of the 2013 IEEE International Test Conference, 2013

Content-driven adaptive computation offloading for energy-aware hybrid distributed video coding.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Content-adaptive reference frame compression based on intra-frame prediction for multiview video coding.
Proceedings of the IEEE International Conference on Image Processing, 2013

An adaptive complexity reduction scheme with fast prediction unit decision for HEVC intra encoding.
Proceedings of the IEEE International Conference on Image Processing, 2013

An adaptive workload management scheme for HEVC encoding.
Proceedings of the IEEE International Conference on Image Processing, 2013

High-throughput interpolation hardware architecture with coarse-grained reconfigurable datapaths for HEVC.
Proceedings of the IEEE International Conference on Image Processing, 2013

Agent-based distributed power management for kilo-core processors.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

AMBER: adaptive energy management for on-chip hybrid video memories.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

MOMA: mapping of memory-intensive software-pipelined applications for systems with multiple memory controllers.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Formal verification of distributed dynamic thermal management.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

ISOMER: integrated selection, partitioning, and placement methodology for reconfigurable architectures.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

DHASER: dynamic heterogeneous adaptation for soft-error resiliency in ASIP-based multi-core systems.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Analyzing the thermal hotspots in FPGA-based embedded systems.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Accurate Thermal-Profile Estimation and Validation for FPGA-Mapped Circuits.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

Message from the chairs.
Proceedings of the 11th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2013

Stress balancing to mitigate NBTI effects in register files.
Proceedings of the 2013 43rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2013

Fast and accurate cache modeling in source-level simulation of embedded software.
Proceedings of the Design, Automation and Test in Europe, 2013

Self-adaptive hybrid dynamic power management for many-core systems.
Proceedings of the Design, Automation and Test in Europe, 2013

Energy-efficient memory hierarchy for motion and disparity estimation in multiview video coding.
Proceedings of the Design, Automation and Test in Europe, 2013

Leveraging variable function resilience for selective software reliability on unreliable hardware.
Proceedings of the Design, Automation and Test in Europe, 2013

CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors.
Proceedings of the Design, Automation and Test in Europe, 2013

Hardware-software collaborative complexity reduction scheme for the emerging HEVC intra encoder.
Proceedings of the Design, Automation and Test in Europe, 2013

An H.264 Quad-FullHD low-latency intra video encoder.
Proceedings of the Design, Automation and Test in Europe, 2013

Pipelets: self-organizing software pipelines for many-core architectures.
Proceedings of the Design, Automation and Test in Europe, 2013

DANCE: distributed application-aware node configuration engine in shared reconfigurable sensor networks.
Proceedings of the Design, Automation and Test in Europe, 2013

Adaptive cache management for a combined SRAM and DRAM cache hierarchy for multi-cores.
Proceedings of the Design, Automation and Test in Europe, 2013

Mapping on multi/many-core systems: survey of current and emerging trends.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Exploiting program-level masking and error propagation for constrained reliability optimization.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

RASTER: runtime adaptive spatial/temporal error resiliency for embedded processors.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Optimizations for configuring and mapping software pipelines in many core systems.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Reliable on-chip systems in the nano-era: lessons learnt and future trends.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Run-time adaption for highly-complex multi-core systems.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

Reducing inter-core cache contention with an adaptive bank mapping policy in DRAM cache.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

Hardware acceleration for programs in SSA form.
Proceedings of the International Conference on Compilers, 2013

Simultaneously optimizing DRAM cache hit latency and miss rate via novel set mapping policies.
Proceedings of the International Conference on Compilers, 2013

Thermal management for dependable on-chip systems.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

3D Video Coding for Embedded Devices - Energy Efficient Algorithms and Architectures.
Springer, ISBN: 978-1-4614-6758-8, 2013

2012
AdNoC: Runtime Adaptive Network-on-Chip Architecture.
IEEE Trans. VLSI Syst., 2012

ECO/ee: Energy-aware Collaborative Organic execution environment for wireless sensor networks.
Proceedings of the 2012 IEEE Wireless Communications and Networking Conference, 2012

Adaptive processor architecture - invited paper.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

A complexity reduction scheme with adaptive search direction and mode elimination for multiview video coding.
Proceedings of the 2012 Picture Coding Symposium, 2012

Work in Progress: Malleable Software Pipelines for Efficient Many-core System Utilization.
Proceedings of the 6th Many-core Applications Research Community (MARC) Symposium. Proceedings of the 6th MARC Symposium, 2012

An adaptive data gathering strategy for target tracking in cluster-based wireless sensor networks.
Proceedings of the 2012 IEEE Symposium on Computers and Communications, 2012

An adaptive data gathering strategy for target tracking in cluster-based wireless sensor networks.
Proceedings of the 2012 IEEE Symposium on Computers and Communications, 2012

Transparent structural online test for reconfigurable systems.
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012

A Reconfigurable Hardware Accelerated Platform for Clustered Wireless Sensor Networks.
Proceedings of the 18th IEEE International Conference on Parallel and Distributed Systems, 2012

A Model Predictive Controller for Frame-Level Rate Control in Multiview Video Coding.
Proceedings of the 2012 IEEE International Conference on Multimedia and Expo, 2012

PATS: A Performance Aware Task Scheduler for Runtime Reconfigurable Processors.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

Dependable embedded systems: The German research foundation DFG priority program SPP 1500.
Proceedings of the 17th IEEE European Test Symposium, 2012

Accurate source-level simulation of embedded software with respect to compiler optimizations.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Power-efficient error-resiliency for H.264/AVC Context-Adaptive Variable Length Coding.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Dynamic cache management in multi-core architectures through run-time adaptation.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Partial online-synthesis for mixed-grained reconfigurable architectures.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Adaptive power management of on-chip video memory for multiview video coding.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Instruction scheduling for reliability-aware compilation.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

HyCoS: hybrid compiled simulation of embedded software with target dependent code.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

A hierarchical control scheme for energy quota distribution in hybrid distributed video coding.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

COOL: control-based optimization of load-balancing for thermal behavior.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

RAISE: Reliability-Aware Instruction SchEduling for unreliable hardware.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Invasive manycore architectures.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

OTERA: Online test strategies for reliable reconfigurable architectures - Invited paper for the AHS-2012 special session "Dependability by reconfigurable hardware".
Proceedings of the 2012 NASA/ESA Conference on Adaptive Hardware and Systems, 2012

2011
Self-Immunity Technique to Improve Register File Integrity Against Soft Errors.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Dynamic Processor Reconfiguration.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Agent-Based Thermal Management Using Real-Time I/O Communication Relocation for 3D Many-Cores.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

Dependable Embedded Systems - Introduction and overview of the DFG SPP-1500.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011

An Empirical Feedback Provider for Multi Core Schedulers.
Proceedings of the 3rd Many-core Applications Research Community (MARC) Symposium. Proceedings of the 3rd MARC Symposium, 2011

RDTS: A Reliable Erasure-Coding Based Data Transfer Scheme for Wireless Sensor Networks.
Proceedings of the 17th IEEE International Conference on Parallel and Distributed Systems, 2011

A multi-level dynamic complexity reduction scheme for multiview video coding.
Proceedings of the 18th IEEE International Conference on Image Processing, 2011

A high-throughput parallel hardware architecture for H.264/AVC CAVLC encoding.
Proceedings of the 18th IEEE International Conference on Image Processing, 2011

Revc: Computationally Reliable Video Coding on unreliable hardware platforms: A case study on error-tolerant H.264/AVC CAVLC entropy coding.
Proceedings of the 18th IEEE International Conference on Image Processing, 2011

A low-power memory architecture with application-aware power management for motion & disparity estimation in Multiview Video Coding.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

System-level application-aware dynamic power management in adaptive pipelined MPSoCs for multimedia.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Run-Time Resource Allocation for Simultaneous Multi-tasking in Multi-core Reconfigurable Processors.
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

Multi-level pipelined parallel hardware architecture for high throughput motion and disparity estimation in Multiview Video Coding.
Proceedings of the Design, Automation and Test in Europe, 2011

Minority-Game-based resource allocation for run-time reconfigurable multi-core processors.
Proceedings of the Design, Automation and Test in Europe, 2011

CARAT: Context-aware runtime adaptive task migration for multi core architectures.
Proceedings of the Design, Automation and Test in Europe, 2011

Dynamic thermal management in 3D multi-core architecture through run-time adaptation.
Proceedings of the Design, Automation and Test in Europe, 2011

mRTS: Run-time system for reconfigurable processors with multi-grained instruction-set extensions.
Proceedings of the Design, Automation and Test in Europe, 2011

Run-time adaptive energy-aware motion and disparity estimation in multiview video coding.
Proceedings of the 48th Design Automation Conference, 2011

Low-power adaptive pipelined MPSoCs for multimedia: an H.264 video encoder case study.
Proceedings of the 48th Design Automation Conference, 2011

SEAL: soft error aware low power scheduling by Monte Carlo state space under the influence of stochastic spatial and temporal dependencies.
Proceedings of the 48th Design Automation Conference, 2011

Reliable software for unreliable hardware: embedded code generation aiming at reliability.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

DistRM: distributed resource management for on-chip many-core systems.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011


Economic learning for thermal-aware power budgeting in many-core architectures.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

Adaptive resource management for simultaneous multitasking in mixed-grained reconfigurable multi-core processors.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

A heterogeneous SoC architecture with embedded virtual FPGA cores and runtime Core Fusion.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

Concepts, architectures, and run-time systems for efficient and adaptive reconfigurable processors.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

Invasive Computing: An Overview.
Proceedings of the Multiprocessor System-on-Chip - Hardware Design and Tool Integration., 2011

DodOrg - A Self-adaptive Organic Many-core Architecture.
Proceedings of the Organic Computing - A Paradigm Shift for Complex Systems, 2011

Agent-Based Thermal Management for Multi-core Architectures.
Proceedings of the Organic Computing - A Paradigm Shift for Complex Systems, 2011

Hardware/Software Architectures for Low-Power Embedded Multimedia Systems.
Springer, ISBN: 978-1-4419-9691-6, 2011

Run-time Adaptation for Reconfigurable Embedded Processors.
Springer, ISBN: 978-1-4419-7411-2, 2011

2010
Optimizing the H.264/AVC Video Encoder Application Structure for Reconfigurable and Application-Specific Platforms.
Signal Processing Systems, 2010

Guest Editorial: Current Trends in Low-Power Design.
ACM Trans. Design Autom. Electr. Syst., 2010

Call for papers ACM transactions on design automation of electronic systems (TODAES) special section on low-power electronics and design.
ACM Trans. Design Autom. Electr. Syst., 2010

Huffman-based code compression techniques for embedded processors.
ACM Trans. Design Autom. Electr. Syst., 2010

Ultra-Low Power Signal Processing [DSP Forum].
IEEE Signal Process. Mag., 2010

Runtime Thermal Management Using Software Agents for Multi- and Many-Core Architectures.
IEEE Design & Test of Computers, 2010

CASES 2009 guest editor's introduction.
Design Autom. for Emb. Sys., 2010

An adaptive early skip mode decision scheme for multiview video coding.
Proceedings of the Picture Coding Symposium, 2010

Power-aware complexity-scalable multiview video coding for mobile devices.
Proceedings of the Picture Coding Symposium, 2010

Selective instruction set muting for energy-aware adaptive processors.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

SETS: Stochastic execution time scheduling for multicore systems by joint state space and Monte Carlo.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Message from the chairs.
Proceedings of the 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia, 2010

An HVS-based Adaptive Computational Complexity Reduction Scheme for H.264/AVC video encoder using Prognostic Early Mode Exclusion.
Proceedings of the Design, Automation and Test in Europe, 2010

enBudget: A Run-Time Adaptive Predictive Energy-Budgeting scheme for energy-aware Motion Estimation in H.264/MPEG-4 AVC video encoder.
Proceedings of the Design, Automation and Test in Europe, 2010

KAHRISMA: A novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array architecture.
Proceedings of the Design, Automation and Test in Europe, 2010

DAGS: Distribution agnostic sequential Monte Carlo scheme for task execution time estimation.
Proceedings of the Design, Automation and Test in Europe, 2010

RMOT: Recursion in model order for task execution time estimation in a software pipeline.
Proceedings of the Design, Automation and Test in Europe, 2010

NeuroNoC: neural network inspired runtime adaptation for an on-chip communication architecture.
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

2009
Security and Dependability of Embedded Systems: A Computer Architects' Perspective.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Non-linear rate control for H.264/AVC video encoder with multiple picture types using image-statistics and motion-based Macroblock Prioritization.
Proceedings of the International Conference on Image Processing, 2009

REMiS: Run-time energy minimization scheme in a reconfigurable processor with dynamic power-gated instruction set.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

TAPE: Thermal-aware agent-based power econom multi/many-core architectures.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

RISPP: A run-time adaptive reconfigurable embedded processor.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

A parallel approach for high performance hardware design of intra prediction in H.264/AVC Video Codec.
Proceedings of the Design, Automation and Test in Europe, 2009

Efficient constant-time entropy decoding for H.264.
Proceedings of the Design, Automation and Test in Europe, 2009

Configurable links for runtime adaptive on-chip communication.
Proceedings of the Design, Automation and Test in Europe, 2009

Cross-architectural design space exploration tool for reconfigurable processors.
Proceedings of the Design, Automation and Test in Europe, 2009

LICT: left-uncompressed instructions compression technique to improve the decoding performance of VLIW processors.
Proceedings of the 46th Design Automation Conference, 2009

MinDeg: a performance-guided replacement policy for run-time reconfigurable accelerators.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

2008
Guest Editorial Special Section on Low-Power Electronics and Design.
IEEE Trans. VLSI Syst., 2008

Efficient Code Compression for Embedded Processors.
IEEE Trans. VLSI Syst., 2008

Efficient Resource Utilization for an Extensible Processor Through Dynamic Instruction Set Adaptation.
IEEE Trans. VLSI Syst., 2008

QoS-supported On-chip Communication for Multi-processors.
International Journal of Parallel Programming, 2008

Dependability and Security Will Change Embedded Computing.
IEEE Computer, 2008

3-tier dynamically adaptive power-aware motion estimator for h.264/AVC video encoding.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

ROAdNoC: runtime observability for an adaptive network on chip architecture.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

FBT: filled buffer technique to reduce code size for VLIW processors.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

A computation- and communication- infrastructure for modular special instructions in a dynamically reconfigurable processor.
Proceedings of the FPL 2008, 2008

Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures.
Proceedings of the Design, Automation and Test in Europe, 2008

Instruction Re-encoding Facilitating Dense Embedded Code.
Proceedings of the Design, Automation and Test in Europe, 2008

Run-time System for an Extensible Embedded Processor with Dynamic Instruction Set.
Proceedings of the Design, Automation and Test in Europe, 2008

ADAM: run-time agent-based distributed application mapping for on-chip communication.
Proceedings of the 45th Design Automation Conference, 2008

Run-time instruction set selection in a transmutable embedded processor.
Proceedings of the 45th Design Automation Conference, 2008

Block cache for embedded systems.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
A Self-Adaptive Extensible Embedded Processor.
Proceedings of the First International Conference on Self-Adaptive and Self-Organizing Systems, 2007

Run-time adaptive on-chip communication scheme.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

An Optimized Application Architecture of the H.264 Video Encoder for Application Specific Platforms.
Proceedings of the 2007 5th Workshop on Embedded Systems for Real-Time Multimedia, 2007

Instruction trace compression for rapid instruction cache simulation.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Efficient code density through look-up table compression.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Instruction Splitting for Efficient Code Compression.
Proceedings of the 44th Design Automation Conference, 2007

RISPP: Rotating Instruction Set Processing Platform.
Proceedings of the 44th Design Automation Conference, 2007

Transaction Specific Virtual Channel Allocation in QoS Supported On-chip Communication.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006
Distance-based recent use (DRU): an enhancement to instruction cache replacement policies for transition energy reduction.
IEEE Trans. VLSI Syst., 2006

A design methodology for application-specific networks-on-chip.
ACM Trans. Embedded Comput. Syst., 2006

Using Shiftable Content Addressable Memories to Double Memory Capacity on Embedded Systems.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Using Lin-Kernighan algorithm for look-up table compression to improve code density.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Bounded arbitration algorithm for QoS-supported on-chip communication.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Digital On-Demand Computing Organism for Real-Time Systems.
Proceedings of the ARCS 2006, 2006

2005
Instruction code mapping for performance increase and energy reduction in embedded computer systems.
IEEE Trans. VLSI Syst., 2005

Approximate arithmetic coding for bus transition reduction in low power designs.
IEEE Trans. VLSI Syst., 2005

A Methodology for Architectural Design of Multimedia Multiprocessor SoCs.
IEEE Design & Test of Computers, 2005

A Unified Architecture for Adaptive Compression of Data and Code on Embedded Systems.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

A methodology for design, modeling, and analysis of networks-on-chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

H.264 HDTV Decoder Using Application-Specific Networks-On-Chip.
Proceedings of the 2005 IEEE International Conference on Multimedia and Expo, 2005

A flexible framework for communication evaluation in SoC design.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Battery-aware instruction generation for embedded processors.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Cypress: Compression and Encryption of Data and Code for Embedded Multimedia Systems.
IEEE Design & Test of Computers, 2004

On-chip networks: A scalable, communication-centric embedded system design paradigm.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

A quantitative study and estimation models for extensible instructions in embedded processors.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

A Case Study in Networks-on-Chip Design for Embedded Video.
Proceedings of the 2004 Design, 2004

Distributed Multimedia System Design: A Holistic Perspective.
Proceedings of the 2004 Design, 2004

MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor.
Proceedings of the 2004 Design, 2004

2003
A dictionary-based en/decoding scheme for low-power data buses.
IEEE Trans. VLSI Syst., 2003

An Overview of Rapid System Prototyping Today.
Design Autom. for Emb. Sys., 2003

Guest Editors' Introduction: Taking on the Embedded System Design Challenge.
IEEE Computer, 2003

Closing the SoC Design Gap.
IEEE Computer, 2003

Specification and Design of Multi-Million Gate SOCs.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

LRU-SEQ: A Novel Replacement Policy for Transition Energy Reduction in Instruction Caches.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

INSIDE: INstruction Selection/Identification & Design Exploration for Extensible Processors.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Enhancing Signal Integrity through a Low-Overhead Encoding Scheme on Address Buses.
Proceedings of the 2003 Design, 2003

Rapid Configuration and Instruction Selection for an ASIP: A Case Study.
Proceedings of the 2003 Design, 2003

CoCo: a hardware/software platform for rapid prototyping of code compression technologies.
Proceedings of the 40th Design Automation Conference, 2003

Multi-parametric improvements for embedded systems using code-placement and address bus coding.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

SEA: fast power estimation for micro-architectures.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Avalanche: an environment for design space exploration and optimization of low-power embedded systems.
IEEE Trans. VLSI Syst., 2002

System-level exploration for Pareto-optimal configurations in parameterized system-on-a-chip.
IEEE Trans. VLSI Syst., 2002

ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

An Adaptive Dictionary Encoding Scheme for SOC Data Buses.
Proceedings of the 2002 Design, 2002

Dynamic Runtime Re-Scheduling Allowing Multiple Implementations of a Task for Platform-Based Designs.
Proceedings of the 2002 Design, 2002

Design of an one-cycle decompression hardware for performance increase in embedded systems.
Proceedings of the 39th Design Automation Conference, 2002

2001
An approach to automated hardware/software partitioning using a flexible granularity that is driven by high-level estimation techniques.
IEEE Trans. VLSI Syst., 2001

Evaluating power consumption of parameterized cache and bus architectures in system-on-a-chip designs.
IEEE Trans. VLSI Syst., 2001

Design and simulation of a pipelined decompression architecture for embedded systems.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

I-CoPES: Fast Instruction Code Placement for Embedded Systems to Improve Performance and Energy Efficiency.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

System-Level Exploration for Pareto-Optimal Configurations in Parameterized Systems-on-a-Chip.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

A2BC: Adaptive Address Bus Coding for Low Power Deep Sub-Micron Designs.
Proceedings of the 38th Design Automation Conference, 2001

Trace-driven system-level power evaluation of system-on-a-chip peripheral cores.
Proceedings of ASP-DAC 2001, 2001

2000
Instruction-based System-level Power Evaluation of System-On-A-Chip Peripheral Cores.
Proceedings of the 13th International Symposium on System Synthesis, 2000

A Decompression Architecture for Low Power Embedded Systems.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Arithmetic Coding for Low Power Embedded System Design.
Proceedings of the Data Compression Conference, 2000

Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design.
Proceedings of the 2000 Design, 2000

Code compression for low power embedded system design.
Proceedings of the 37th Conference on Design Automation, 2000

Code compression as a variable in hardware/software co-design.
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

A hybrid approach for core-based system-level power modeling.
Proceedings of ASP-DAC 2000, 2000

1999
Interface and cache power exploration for core-based embedded system design.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

A Methodology for Minimizing Power Dissipation of Embedded Systems through Hardware/Software Partitioning.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

A Low Power Hardware/Software Partitioning Approach for Core-Based Embedded Systems.
Proceedings of the 36th Conference on Design Automation, 1999

1998
A Framework for Estimation and Minimizing Energy Dissipation of Embedded HW/SW Systems.
Proceedings of the 35th Conference on Design Automation, 1998

Energy-conscious HW/SW-partitioning of embedded systems: a case study on an MPEG-2 encoder.
Proceedings of the Sixth International Workshop on Hardware/Software Codesign, 1998

High-Level Estimation Techniques for Usage in Hardware/Software Co-Design.
Proceedings of the ASP-DAC '98, 1998

1997
A Hardware/Software Partitioner Using a Dynamically Determined Granularity.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Automatisierte Hardware-Software-Partitionierung im Entwurf integrierter Echtzeitsysteme.
PhD thesis, 1996

The COSYMA environment for hardware/software cosynthesis of small embedded systems.
Microprocessors and Microsystems - Embedded Hardware Design, 1996

The Interplay of Run-Time Estimation and Granularity in HW/SW Partitioning.
Proceedings of the Forth International Workshop on Hardware/Software Codesign, 1996

1995
A path-based technique for estimating hardware runtime in HW/SW-cosynthesis.
Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995

1994
Adaptation of partitioning and high-level synthesis in hardware/software co-synthesis.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

An approach to the adaptation of estimated cost parameters in the COSYMA system.
Proceedings of the Third International Workshop on Hardware/Software Codesign, 1994

1993
Hardware-Software Cosynthesis for Microcontrollers.
IEEE Design & Test of Computers, 1993

Fast Timing Analysis for Hardware-Software Co-Synthesis.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993


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