Jorgen Peddersen

Roshan G. Ragel

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2015

RAPITIMATE: Rapid performance estimation of pipelined processing systems containing shared memory.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Sequential C-code to distributed pipelined heterogeneous MPSoC synthesis for streaming applications.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

E-pipeline: elastic hardware/software pipelines on a many-core fabric.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Speeding up single pass simulation of PLRUt caches.

[BibT_eX]

[DOI]

Josef Schneider

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

MASH{fifo}: A Hardware-Based Multiple Cache Simulator for Rapid FIFO Cache Analysis.

[BibT_eX]

[DOI]

Josef Schneider

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

A scorchingly fast FPGA-based Precise L1 LRU cache simulator.

[BibT_eX]

[DOI]

Josef Schneider

Swarnalatha Radhakrishnan

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

SDG2KPN: System Dependency Graph to function-level KPN generation of legacy code for MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

A double-width algorithmic balancing to prevent power analysis Side Channel Attacks in AES.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

DRMA: dynamically reconfigurable MPSoC architecture.

[BibT_eX]

[DOI]

Kewal K. Saluja

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2012

A Rapid Methodology for Multi-mode Communication Circuit Generation.

[BibT_eX]

[DOI]

Liang Tang

Proceedings of the 25th International Conference on VLSI Design, 2012

2011

Realizing Cycle Accurate Processor Memory Simulation via Interface Abstraction.

[BibT_eX]

[DOI]

Su Myat Min

Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation technique.

[BibT_eX]

[DOI]

Mohammad Shihabul Haque

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010

LOP: A packet classification architecture with higher throughput and lower power consumption than TCAM.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2010

ACS: Automatic Converter Synthesis for SoC Bus Protocols.

[BibT_eX]

[DOI]

Karin Avnit

Arcot Sowmya

Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2010

Improved Architectures for Range Encoding in Packet Classification System.

[BibT_eX]

[DOI]

Proceedings of The Ninth IEEE International Symposium on Networking Computing and Applications, 2010

RACE: A Rapid, ArChitectural Simulation and Synthesis Framework for Embedded Processors.

[BibT_eX]

[DOI]

Proceedings of the Distributed, Parallel and Biologically Inspired Systems, 2010

Dueling CLOCK: Adaptive cache replacement policy based on the CLOCK algorithm.

[BibT_eX]

[DOI]

Andhi Janapsatya

Aleksandar Ignjatovic

Proceedings of the Design, Automation and Test in Europe, 2010

DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy.

[BibT_eX]

[DOI]

Mohammad Shihabul Haque

Andhi Janapsatya

Proceedings of the Design, Automation and Test in Europe, 2010

SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy.

[BibT_eX]

[DOI]

Mohammad Shihabul Haque

Andhi Janapsatya

Proceedings of the 47th Design Automation Conference, 2010

2009

LOP_RE: Range encoding for low power packet classification.

[BibT_eX]

[DOI]

Proceedings of the 34th Annual IEEE Conference on Local Computer Networks, 2009

LOP: a novel SRAM-based architecture for low power and high throughput packet classification.

[BibT_eX]

[DOI]

Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

2008

Energy Driven Application Self-Adaptation at Run-time.

[BibT_eX]

[DOI]

J. Comput., 2008

Low-Impact Processor for Dynamic Runtime Power Management.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2008

2007

Energy Driven Application SelfAdaptation.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time.

[BibT_eX]

[DOI]