Andrew Wolfe

According to our database1, Andrew Wolfe authored at least 39 papers between 1988 and 2002.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2002
Guest Editors' Introduction: Hot Chips 13.
IEEE Micro, 2002

2001
Emerging applications for the connected home.
Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

2000
An Experimental Analysis of Digital Video Library Servers.
Multimedia Syst., 2000

A Superscalar 3D Graphics Engine.
J. Instruction-Level Parallelism, 2000

1999
Performance estimation of embedded software with instruction cache modeling.
ACM Trans. Design Autom. Electr. Syst., 1999

1998
A methodology to evaluate memory architecture design tradeoffs for video signal processors.
IEEE Trans. Circuits Syst. Video Techn., 1998

A design study of a 0.25-μm video signal processor.
IEEE Trans. Circuits Syst. Video Techn., 1998

A Fast Asynchronous Huffman Decoder for Compressed-Code Embedded Processors.
Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March, 1998

1997
On the balance of VLIW architectures.
Journal of Systems Architecture, 1997

Challenges to Combining General-Purpose and Multimedia Processors.
IEEE Computer, 1997

Available Parallelism in Video Applications.
Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, 1997

An Approach to Network Caching for Multimedia Objects.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Datapath Design for a VLIW Video Signal Processor.
Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture (HPCA '97), 1997

Combining General-Purpose and Multimedia in One Package: Challenges and Opportunities.
Proceedings of the 30th Annual Hawaii International Conference on System Sciences (HICSS-30), 1997

Cinderella: A Retargetable Environment for Performance Analysis of Real-Time Software.
Proceedings of the Euro-Par '97 Parallel Processing, 1997

Branch Libraries for Multimedia Repositories (Poster).
Proceedings of the 2nd ACM International Conference on Digital Libraries, 1997

A High-Speed Asynchronous Decompression Circuit for Embedded Processors.
Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97), 1997

1996
Instruction level power analysis and optimization of software.
VLSI Signal Processing, 1996

Issues for low-power CAD tools: A system-level design study.
Design Autom. for Emb. Sys., 1996

Lessons from the design of a PC-based private branch exchange.
Design Autom. for Emb. Sys., 1996

Cache modeling for real-time software: beyond direct mapped instruction caches.
Proceedings of the 17th IEEE Real-Time Systems Symposium (RTSS '96), 1996

New Challenges for Video Servers: Performance of Non-Linear Applications under User Choice.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Functionality Distribution on a Superscalar Architecture.
Proceedings of the Euro-Par '96 Parallel Processing, 1996

Load Balancing in Superscalar Architectures.
Proceedings of the 22rd EUROMICRO Conference '96, 1996

Opportunities and Obstacles in Low-Power System-Level CAD.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Efficient Microarchitecture Modeling and Path Analysis for Real-Time Software.
Proceedings of the 16th IEEE Real-Time Systems Symposium, 1995

A case study in low-power system-level design.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

VLSI issues in memory-system design for video signal processors.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Video as Scholary Material in the Digital Library.
Proceedings of the Digital Libraries, Research and Technology Advances, 1995

1994
Power analysis of embedded software: a first step towards software power minimization.
IEEE Trans. VLSI Syst., 1994

The effect of compiler-flag tuning on SPEC benchmark performance.
SIGARCH Computer Architecture News, 1994

Compression of Embedded System Programs.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

TigerSwitch: a case study in embedded computing system design.
Proceedings of the Third International Workshop on Hardware/Software Codesign, 1994

1993
Two-ported cache alternatives for superscalar processors.
Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993

A Split Data Cache for Superscalar Processors.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

1992
Executing compressed programs on an embedded RISC architecture.
Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992

1991
A Variable Instruction Stream Extension to the VLIW Architecture.
Proceedings of the ASPLOS-IV Proceedings, 1991

1988
Flexible processors: a promising application-specific processor design approach.
Proceedings of the 21st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1988, San Diego, California, USA, November 28, 1988

The White Dwarf: A High-Performance Application-Specific Processor.
Proceedings of the 15th Annual International Symposium on Computer Architecture, 1988


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