Maurício Breternitz

According to our database, Maurício Breternitz authored at least 49 papers between 1988 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

ULEEN: A Novel Architecture for Ultra-low-energy Edge Neural Networks.

Zachary Susskind, Aman Arora, Igor D. S. Miranda, Alan T. L. Bacellar, Luis A. Q. Villon, Rafael Fontella Katopodis, Leandro Santiago de Araújo, Diego L. C. Dutra, Priscila M. V. Lima, Felipe M. G. França, Maurício Breternitz, Lizy K. John

ACM Trans. Archit. Code Optim., December, 2023

A conditional branch predictor based on weightless neural networks.

Luis A. Q. Villon, Zachary Susskind, Alan T. L. Bacellar, Igor D. S. Miranda, Leandro Santiago de Araújo, Priscila M. V. Lima, Maurício Breternitz, Lizy K. John, Felipe M. G. França, Diego Leonel Cadette Dutra

Neurocomputing, October, 2023

Dendrite-inspired Computing to Improve Resilience of Neural Networks to Faults in Emerging Memory Technologies.

Lizy K. John, Felipe M. G. França, Subhasish Mitra, Zachary Susskind, Priscila M. V. Lima, Igor D. S. Miranda, Eugene B. John, Diego L. C. Dutra, Maurício Breternitz

Proceedings of the IEEE International Conference on Rebooting Computing, 2023

An FPGA-Based Weightless Neural Network for Edge Network Intrusion Detection.

Zachary Susskind, Aman Arora, Alan T. L. Bacellar, Diego Leonel Cadette Dutra, Igor D. S. Miranda, Maurício Breternitz, Priscila M. V. Lima, Felipe M. G. França, Lizy K. John

Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

COIN: Combinational Intelligent Networks.

Igor D. S. Miranda, Aman Arora, Zachary Susskind, Josias S. A. Souza, Mugdha P. Jadhao, Luis A. Q. Villon, Diego L. C. Dutra, Priscila M. V. Lima, Felipe M. G. França, Maurício Breternitz, Lizy K. John

Proceedings of the 34th IEEE International Conference on Application-specific Systems, 2023

2022

A WiSARD-based conditional branch predictor.

Luis A. Q. Villon, Zachary Susskind, Alan T. L. Bacellar, Igor D. S. Miranda, Leandro Santiago de Araújo, Priscila M. V. Lima, Maurício Breternitz Jr., Lizy K. John, Felipe M. G. França, Diego Leonel Cadette Dutra

Proceedings of the 30th European Symposium on Artificial Neural Networks, 2022

Pruning Weightless Neural Networks.

Zachary Susskind, Alan T. L. Bacellar, Aman Arora, Luis A. Q. Villon, Renan Mendanha, Leandro Santiago de Araújo, Diego Leonel Cadette Dutra, Priscila M. V. Lima, Felipe M. G. França, Igor D. S. Miranda, Maurício Breternitz Jr., Lizy K. John

Proceedings of the 30th European Symposium on Artificial Neural Networks, 2022

Distributive Thermometer: A New Unary Encoding for Weightless Neural Networks.

Alan T. L. Bacellar, Zachary Susskind, Luis A. Q. Villon, Igor D. S. Miranda, Leandro Santiago de Araújo, Diego Leonel Cadette Dutra, Maurício Breternitz Jr., Lizy K. John, Priscila M. V. Lima, Felipe M. G. França

Proceedings of the 30th European Symposium on Artificial Neural Networks, 2022

LogicWiSARD: Memoryless Synthesis of Weightless Neural Networks.

Igor D. S. Miranda, Aman Arora, Zachary Susskind, Luis Armando Quintanilla Villon, Rafael Fontella Katopodis, Diego Leonel Cadette Dutra, Leandro Santiago de Araújo, Priscila M. V. Lima, Felipe M. G. França, Lizy K. John, Maurício Breternitz

Proceedings of the 33rd IEEE International Conference on Application-specific Systems, 2022

Weightless Neural Networks for Efficient Edge Inference.

Zachary Susskind, Aman Arora, Igor D. S. Miranda, Luis Armando Quintanilla Villon, Rafael Fontella Katopodis, Leandro Santiago de Araújo, Diego Leonel Cadette Dutra, Priscila M. V. Lima, Felipe M. G. França, Maurício Breternitz, Lizy K. John

Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2022

2021

Efficiency and scalability of multi-lane capsule networks (MLCN).

Vanderson Martins do Rosario, Maurício Breternitz Jr., Edson Borin

J. Parallel Distributed Comput., 2021

Smart selection of optimizations in dynamic compilers.

Vanderson Martins do Rosario, Anderson Faustino da Silva, Thais Aparecida Silva Camacho, Otávio Oliveira Napoli, Maurício Breternitz, Edson Borin

Concurr. Comput. Pract. Exp., 2021

2020

Weightless Neural Networks as Memory Segmented Bloom Filters.

Leandro Santiago, Letícia Dias Verona, Fábio Medeiros Rangel, Fabrício Firmino de Faria, Daniel S. Menasché, Wouter Caarls, Maurício Breternitz Jr., Sandip Kundu, Priscila M. V. Lima, Felipe M. G. França

Neurocomputing, 2020

A unified model for accelerating unsupervised iterative re-ranking algorithms.

Flávia Pisani, Lucas Pascotti Valem, Daniel Carlos Guimarães Pedronette, Ricardo da Silva Torres, Edson Borin, Maurício Breternitz Jr.

Concurr. Comput. Pract. Exp., 2020

2019

The Multi-Lane Capsule Network.

Vanderson Martins do Rosario, Edson Borin, Maurício Breternitz

IEEE Signal Process. Lett., 2019

The Multi-Lane Capsule Network (MLCN).

Vanderson Martins do Rosario, Edson Borin, Maurício Breternitz Jr.

CoRR, 2019

Memory Efficient Weightless Neural Network using Bloom Filter.

Leandro Santiago de Araújo, Letícia Dias Verona, Fábio Medeiros Rangel, Fabrício Firmino de Faria, Daniel Sadoc Menasché, Wouter Caarls, Maurício Breternitz, Sandip Kundu, Priscila Machado Vieira Lima, Felipe Maia Galvão França

Proceedings of the 27th European Symposium on Artificial Neural Networks, 2019

2018

ComP-net: command processor networking for efficient intra-kernel communications on GPUs.

Michael LeBeane, Khaled Hamidouche, Brad Benton, Maurício Breternitz, Steven K. Reinhardt, Lizy K. John

Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, 2018

2017

GPU triggered networking for intra-kernel communications.

Michael LeBeane, Khaled Hamidouche, Brad Benton, Maurício Breternitz, Steven K. Reinhardt, Lizy K. John

Proceedings of the International Conference for High Performance Computing, 2017

2016

HadoopCL2: Motivating the Design of a Distributed, Heterogeneous Programming System With Machine-Learning Applications.

Max Grossman, Maurício Breternitz Jr., Vivek Sarkar

IEEE Trans. Parallel Distributed Syst., 2016

Extended task queuing: active messages for heterogeneous systems.

Michael LeBeane, Brandon Potter, Abhisek Pan, Alexandru Dutu, Vinay Agarwala, Wonchan Lee, Deepak Majeti, Bibek Ghimire, Eric Van Tassell, Samuel Wasmundt, Brad Benton, Maurício Breternitz, Michael L. Chu, Mithuna Thottethodi, Lizy K. John, Steven K. Reinhardt

Proceedings of the International Conference for High Performance Computing, 2016

PY-PITS: A Scalable Python Runtime System for the Computation of Partially Idempotent Tasks.

Edson Borin, Caian Benedicto, Ian L. Rodrigues, Flavia Pisani, Martin Tygel, Maurício Breternitz

Proceedings of the 2016 International Symposium on Computer Architecture and High Performance Computing Workshops, 2016

2014

Adaptive global power optimization for Web servers.

Leonardo Piga, Reinaldo A. Bergamaschi, Maurício Breternitz, Sandro Rigo

J. Supercomput., 2014

Microcode Compression Using Structured-Constrained Clustering.

Edson Borin, Guido Araujo, Maurício Breternitz Jr., Youfeng Wu

Int. J. Parallel Program., 2014

Implementation and evaluation of deep neural networks (DNN) on mainstream heterogeneous systems.

Junli Gu, Maohua Zhu, Zhitao Zhou, Feng Zhang, Zhen Lin, Qianfeng Zhang, Maurício Breternitz

Proceedings of the Asia-Pacific Workshop on Systems, 2014

2013

Image Re-ranking Acceleration on GPUs.

Daniel Carlos Guimarães Pedronette, Ricardo da Silva Torres, Edson Borin, Maurício Breternitz Jr.

Proceedings of the 25th International Symposium on Computer Architecture and High Performance Computing, 2013

HadoopCL: MapReduce on Distributed Heterogeneous Platforms through Seamless Integration of Hadoop and OpenCL.

Max Grossman, Maurício Breternitz Jr., Vivek Sarkar

Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

2012

Cloud Workload Analysis with SWAT.

Maurício Breternitz, Keith Lowery, Anton Charnoff, Patryk Kaminski, Leonardo Piga

Proceedings of the IEEE 24th International Symposium on Computer Architecture and High Performance Computing, 2012

Efficient Image Re-Ranking Computation on GPUs.

Daniel Carlos Guimarães Pedronette, Ricardo da Silva Torres, Edson Borin, Maurício Breternitz Jr.

Proceedings of the 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, 2012

2011

Structure-Constrained Microcode Compression.

Edson Borin, Guido Araujo, Maurício Breternitz Jr., Youfeng Wu

Proceedings of the 23rd International Symposium on Computer Architecture and High Performance Computing, 2011

LAR-CC: Large atomic regions with conditional commits.

Edson Borin, Youfeng Wu, Maurício Breternitz Jr., Cheng Wang

Proceedings of the CGO 2011, 2011

2010

TAO: two-level atomicity for dynamic binary optimizations.

Edson Borin, Youfeng Wu, Cheng Wang, Wei Liu, Maurício Breternitz Jr., Shiliang Hu, Esfir Natanzon, Shai Rotem, Roni Rosner

Proceedings of the CGO 2010, 2010

2008

A Segmented Bloom Filter Algorithm for Efficient Predictors.

Maurício Breternitz Jr., Gabriel H. Loh, Bryan Black, Jeff Rupley, Peter G. Sassone, Wesley Attrot, Youfeng Wu

Proceedings of the 20th International Symposium on Computer Architecture and High Performance Computing, 2008

2007

Impacts of Multiprocessor Configurations on Workloads in Bioinformatics.

Youfeng Wu, Maurício Breternitz Jr., Victor Ying

Proceedings of the 19th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), 2007

StarDBT: An Efficient Multi-platform Dynamic Binary Translation System.

Cheng Wang, Shiliang Hu, Ho-Seop Kim, Sreekumar R. Nair, Maurício Breternitz Jr., Zhiwei Ying, Youfeng Wu

Proceedings of the Advances in Computer Systems Architecture, 2007

2006

Clustering-Based Microcode Compression.

Edson Borin, Maurício Breternitz Jr., Youfeng Wu, Guido Araujo

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

2005

Enhanced code density of embedded CISC processors with echo technology.

Youfeng Wu, Maurício Breternitz Jr., Herbert H. J. Hum, Ramesh V. Peri, Jay Pickett

Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

2004

The Accuracy of Initial Prediction in Two-Phase Dynamic Binary Translators.

Youfeng Wu, Maurício Breternitz Jr., Justin Quek, Orna Etzion, Jesse Fang

Proceedings of the 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 2004

Continuous Trip Count Profiling for Loop Optimizations in Two-Phase Dynamic Binary Translato.

Youfeng Wu, Maurício Breternitz Jr., Tevi Devor

Proceedings of the 8th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-8 2004), 2004

2003

Compilation, Architectural Support, and Evaluation of SIMD Graphics Pipeline Programs on a General-Purpose CPU.

Maurício Breternitz Jr., Herbert H. J. Hum, Sanjeev Kumar

Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques (PACT 2003), 27 September, 2003

1997

Enhanced Compression Techniques to Simplify Programm Decompression and Execution.

Maurício Breternitz Jr., Roger Smith

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1996

Design Tradeoffs and Experience with Motorola PowerPC? Migration Tool.

Maurício Breternitz Jr., A. Manikonda, M. Ommerman, W. Su, A. Thornto

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Motorola PowerPC Migration Tools - Emulation and Translation.

Tariq Afzal, Maurício Breternitz Jr., M. Kacher, S. Menyhert, M. Ommerman, W. Su

Proceedings of the Forty-First IEEE Computer Society International Conference: Technologies for the Information Superhighway, 1996

1995

Solutions and debugging for data consistency in multiprocessors with noncoherent caches.

David Bernstein, Maurício Breternitz Jr., Ahmed Gheith, Bilha Mendelson

Int. J. Parallel Program., 1995

1994

An Optimal Asynchronous Scheduling Algorithm for Software Cache Consistence.

Barbara Simons, Vivek Sarkar, Maurício Breternitz Jr., Michael Lai

Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994

1991

Implementation Optimization Techniques for Architecture Synthesis of Application-Specific Processors.

Maurício Breternitz Jr., John Paul Shen

Proceedings of the 24th Annual IEEE/ACM International Symposium on Microarchitecture, 1991

1990

Architecture Synthesis of High-Performance Application-Specific Processors.

Maurício Breternitz Jr., John Paul Shen

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1988

Organization of array data for concurrent memory access.

Maurício Breternitz Jr., John Paul Shen

Proceedings of the 21st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1988, San Diego, California, USA, November 28, 1988

The White Dwarf: A High-Performance Application-Specific Processor.

Andrew Wolfe, Maurício Breternitz Jr., Chriss Stephens, A. L. Ting, David Blair Kirk, Ronald P. Bianchini Jr., John Paul Shen

Proceedings of the 15th Annual International Symposium on Computer Architecture, 1988