Anirban Sengupta
This page is a disambiguation page, it actually contains mutiple papers from persons of the same or a similar name.
Known people with the same name:
- Anirban Sengupta 001 (Jadapur University, Kolkata, India)
- Anirban Sengupta 002 (Vanderbilt University Institute of Imaging Science, Nashville, TN, USA)
- Anirban Sengupta 003 (Indian Institute of Technology Indore, Indore, India)
- Anirban Sengupta 004 (Sikkim Manipal Institute of Technology, SMU, Sikkim, India)
Bibliography
2021
IEEE Trans. Intell. Transp. Syst., 2021
2018
Effect of NBTI stress on DSP cores used in CE devices: threat model and performance estimation.
IET Comput. Digit. Tech., 2018
Integrating Compiler Driven Transformation and Simulated Annealing Based Floorplan for Optimized Transient Fault Tolerant DSP Cores.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018
2017
Hardware Vulnerabilities and Their Effects on CE Devices: Design for Security Against Trojans [Hardware Matters].
IEEE Consumer Electron. Mag., 2017
IEEE Consumer Electron. Mag., 2017
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017
Comprehensive Operation Chaining Based Schedule Delay Estimation During High Level Synthesis.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017
A Quantitative Methodology for Cloud Security Risk Assessment.
Proceedings of the CLOSER 2017, 2017
2016
Soft IP Core Design Resiliency Against Terrestrial Transient Faults for CE Products [Hardware Matters].
IEEE Consumer Electron. Mag., 2016
Evolution of the IP Design Process in the Semiconductor/EDA Industry Hardware Matters.
IEEE Consumer Electron. Mag., 2016
IEEE Consumer Electron. Mag., 2016
Generating Multi-cycle and Multiple Transient Fault Resilient Design During Physically Aware High Level Synthesis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016
2014
A two-phase quantitative methodology for enterprise information security risk analysis.
Comput. Syst. Sci. Eng., 2014
Swarm Intelligence Driven Simultaneous Adaptive Exploration of Datapath and Loop Unrolling Factor during Area-Performance Tradeoff.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
PSDSE: Particle Swarm Driven Design Space Exploration of Architecture and Unrolling Factors for Nested Loops in High Level Synthesis.
Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014
Time Varying vs. Fixed Acceleration Coefficient PSO Driven Exploration during High Level Synthesis: Performance and Quality Assessment.
Proceedings of the 2014 International Conference on Information Technology, 2014
2011
Rapid design space exploration by hybrid fuzzy search approach for optimal architecture determination of multi objective computing systems.
Microelectron. Reliab., 2011
Multi-objective efficient design space exploration and architectural synthesis of an application specific processor (ASP).
Microprocess. Microsystems, 2011
Integrated scheduling, allocation and binding in High Level Synthesis using multi structure genetic algorithm based design space exploration.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
2010
A high level synthesis design flow with a novel approach for efficient design space exploration in case of multi-parametric optimization objective.
Microelectron. Reliab., 2010
A framework for fast design space exploration using fuzzy search for VLSI computing Architectures.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010