Ankur Srivastava

According to our database1, Ankur Srivastava authored at least 167 papers between 2000 and 2021.

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Bibliography

2021
Ising-FPGA: A Spintronics-based Reconfigurable Ising Model Solver.
ACM Trans. Design Autom. Electr. Syst., 2021

Evaluating the Security of Delay-Locked Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Enhancing Processor Design Obfuscation Through Security-Aware On-Chip Memory and Data Path Design.
IACR Cryptol. ePrint Arch., 2021

A Resource Binding Approach to Logic Obfuscation.
IACR Cryptol. ePrint Arch., 2021

Robust and Attack Resilient Logic Locking with a High Application-Level Impact.
CoRR, 2021

2020
Keynote: A Disquisition on Logic Locking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Energy-efficient Design of MTJ-based Neural Networks with Stochastic Computing.
ACM J. Emerg. Technol. Comput. Syst., 2020

Strong Anti-SAT: Secure and Effective Logic Locking.
IACR Cryptol. ePrint Arch., 2020

GANRED: GAN-based Reverse Engineering of DNNs via Cache Side-Channel.
IACR Cryptol. ePrint Arch., 2020

A Survey on Neural Trojans.
IACR Cryptol. ePrint Arch., 2020

Hardware-Assisted Intellectual Property Protection of Deep Learning Models.
IACR Cryptol. ePrint Arch., 2020

Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking.
CoRR, 2020

DRAMsim3: A Cycle-Accurate, Thermal-Capable DRAM Simulator.
IEEE Comput. Archit. Lett., 2020

ObfusGEM: Enhancing Processor Design Obfuscation Through Security-Aware On-Chip Memory and Data Path Design.
Proceedings of the MEMSYS 2020: The International Symposium on Memory Systems, 2020

Spintronics-based Reconfigurable Ising Model Architecture.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

StatSAT: A Boolean Satisfiability based Attack on Logic-Locked Probabilistic Circuits.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
Reducing Timing Side-Channel Information Leakage Using 3D Integration.
IEEE Trans. Dependable Secur. Comput., 2019

Enhanced Phase-Driven Q-Learning-Based DRM for Multicore Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Anti-SAT: Mitigating SAT Attack on Logic Locking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

In Situ Stochastic Training of MTJ Crossbars With Machine Learning Algorithms.
ACM J. Emerg. Technol. Comput. Syst., 2019

Secure and Effective Logic Locking for Machine Learning Applications.
IACR Cryptol. ePrint Arch., 2019

Hardware-Software Co-Design Based Obfuscation of Hardware Accelerators.
IACR Cryptol. ePrint Arch., 2019

Memory Locking: An Automated Approach to Processor Design Obfuscation.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Mitigating Reverse Engineering Attacks on Deep Neural Networks.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

2018
A Combined Optimization-Theoretic and Side- Channel Approach for Attacking Strong Physical Unclonable Functions.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Data Driven Optimizations for MTJ based Stochastic Computing.
CoRR, 2018

HMCTherm: a cycle-accurate HMC simulator integrated with detailed power and thermal simulation.
Proceedings of the International Symposium on Memory Systems, 2018

Value-driven Synthesis for Neural Network ASICs.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

In-situ Stochastic Training of MTJ Crossbar based Neural Networks.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

TimingSAT: timing profile embedded SAT attack.
Proceedings of the International Conference on Computer-Aided Design, 2018

GPU obfuscation: attack and defense strategies.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Low-Power Clock Tree Synthesis for 3D-ICs.
ACM Trans. Design Autom. Electr. Syst., 2017

TSV-Based 3-D ICs: Design Methods and Tools.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Correlation Power Analysis Attack against STT-MRAM Based Cyptosystems.
IACR Cryptol. ePrint Arch., 2017

Security-Aware 2.5D Integrated Circuit Design Flow Against Hardware IP Piracy.
Computer, 2017

Analytical global sensitivity analysis with Gaussian processes.
Artif. Intell. Eng. Des. Anal. Manuf., 2017

Power optimizations in MTJ-based Neural Networks through Stochastic Computing.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Introducing TFUE: The trusted foundry and untrusted employee model in IC supply chain security.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A 0.42V high bandwidth synthesizable parallel access smart memory fabric for computer vision.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Detachable modular robot capable of cooperative climbing and multi agent exploration.
Proceedings of the 2017 IEEE International Conference on Robotics and Automation, 2017

Neural Trojans.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Template Attack Based Deobfuscation of Integrated Circuits.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Exploring timing side-channel attacks on path-ORAMs.
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

Design Space Modeling and Simulation for Physically Constrained 3D CPUs.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Phase-driven Learning-based Dynamic Reliability Management For Multi-core Processors.
Proceedings of the 54th Annual Design Automation Conference, 2017

Delay Locking: Security Enhancement of Logic Locking against IC Counterfeiting and Overproduction.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Unlocking the True Potential of 3-D CPUs With Microfluidic Cooling.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Security and Vulnerability Implications of 3D ICs.
IEEE Trans. Multi Scale Comput. Syst., 2016

On Reverse Engineering-Based Hardware Trojan Detection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Mitigating SAT Attack on Logic Locking.
IACR Cryptol. ePrint Arch., 2016

Thermoelectric Codesign of 3-D CPUs and Embedded Microfluidic Pin-Fin Heatsinks.
IEEE Des. Test, 2016

2.5D/3D Integration Technologies for Circuit Obfuscation.
Proceedings of the 17th International Workshop on Microprocessor and SOC Test and Verification, 2016

Post-Placement Optimization for Thermal-Induced Mechanical Stress Reduction.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Electromigration-aware placement for 3D-ICs.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Voltage Noise Induced DRAM Soft Error Reduction Technique for 3D-CPUs.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

An optimization-theoretic approach for attacking physical unclonable functions.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Physical Design of 3D FPGAs Embedded with Micro-channel-based Fluidic Cooling.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

ECO Based Placement and Routing Framework for 3D FPGAs with Micro-fluidic Cooling.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

2015
Modeling and Layout Optimization for Tapered TSVs.
IEEE Trans. Very Large Scale Integr. Syst., 2015

TSV Replacement and Shield Insertion for TSV-TSV Coupling Reduction in 3-D Global Placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Temperature Tracking: Toward Robust Run-Time Detection of Hardware Trojans.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Hybrid Bayesian Solution to NASA Langley Research Center Multidisciplinary Uncertainty Quantification Challenge.
J. Aerosp. Inf. Syst., 2015

3D Integration: New opportunities in defense against cache-timing side-channel attacks.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

A security-aware design scheme for better hardware Trojan detection sensitivity.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

Electromigration-aware Clock Tree Synthesis for TSV-based 3D-ICs.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Security-Aware Design Flow for 2.5D IC Technology.
Proceedings of the 5th International Workshop on Trustworthy Embedded Devices, 2015

2014
Statistical Framework for Designing On-Chip Thermal Sensing Infrastructure in Nanoscale Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Optimized Micro-Channel Design for Stacked 3-D-ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

A geometric approach to chip-scale TSV shield placement for the reduction of TSV coupling in 3D-ICs.
Integr., 2014

On application of one-class SVM to reverse engineering-based hardware Trojan detection.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Coupling-aware force driven placement of TSVs and shields in 3D-IC layouts.
Proceedings of the International Symposium on Physical Design, 2014

Unlocking the true potential of 3D CPUs with micro-fluidic cooling.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Gated low-power clock tree synthesis for 3D-ICs.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

A compliant multi-module robot for climbing big step-like obstacles.
Proceedings of the 2014 IEEE International Conference on Robotics and Automation, 2014

A Secure Algorithm for Task Scheduling against Side-channel Attacks.
Proceedings of the 4th International Workshop on Trustworthy Embedded Devices, 2014

2013
Dynamic Thermal Management Under Soft Thermal Constraints.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Thermal-aware sensor scheduling for distributed estimation.
ACM Trans. Sens. Networks, 2013

Resource-aware architectures for adaptive particle filter based visual target tracking.
ACM Trans. Design Autom. Electr. Syst., 2013

Energy- and Thermal-Aware Video Coding via Encoder/Decoder Workload Balancing.
ACM Trans. Embed. Comput. Syst., 2013

Improving the Quality of Delay-Based PUFs via Optical Proximity Correction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Co-design of micro-fluidic heat sink and thermal through-silicon-vias for cooling of three-dimensional integrated circuit.
IET Circuits Devices Syst., 2013

Micro-Fluidic Cooling for Stacked 3D-ICs: Fundamentals, Modeling and Design.
Adv. Comput., 2013

Temperature tracking: an innovative run-time approach for hardware Trojan detection.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Co-optimization of TSV assignment and micro-channel placement for 3D-ICs.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Thermal stress aware 3D-IC statistical static timing analysis.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Online TSV health monitoring and built-in self-repair to overcome aging.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

High performance 3D stacked DRAM processor architectures with micro-fluidic cooling.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

Detailed electrical and reliability study of tapered TSVs.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012
Thermal and Power-Aware Task Scheduling and Data Placement for Storage Centric Datacenters.
Proceedings of the Handbook of Energy-Aware and Green Computing - Two Volume Set., 2012

Accelerating Gate Sizing Using Graphics Processing Units.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Learning Air-Data Parameters for Flush Air Data Sensing Systems.
J. Aerosp. Comput. Inf. Commun., 2012

Hybrid 3D-IC Cooling System Using Micro-fluidic Cooling and Thermal TSVs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Manipulating Manufacturing Variations for Better Silicon-Based Physically Unclonable Functions.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

TSV-constrained micro-channel infrastructure design for cooling stacked 3D-ICs.
Proceedings of the International Symposium on Physical Design, 2012

On improving the uniqueness of silicon-based physically unclonable functions via optical proximity correction.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Accurate Temperature Estimation Using Noisy Thermal Sensors for Gaussian and Non-Gaussian Cases.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Unified datacenter power management considering on-chip and air temperature constraints.
Sustain. Comput. Informatics Syst., 2011

Energy-aware and quality-scalable data placement and retrieval for disks in video server environments.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Adaptable architectures for distributed visual target tracking.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Statistical characterization of chip power behavior at post-fabrication stage.
Proceedings of the 2011 International Green Computing Conference and Workshops, 2011

Leakage-aware Kalman filter for accurate temperature tracking.
Proceedings of the 2011 International Green Computing Conference and Workshops, 2011

Liquid cooling for 3D-ICs.
Proceedings of the 2011 International Green Computing Conference and Workshops, 2011

Energy-aware video storage and retrieval in server environments.
Proceedings of the 2011 International Green Computing Conference and Workshops, 2011

Resource-aware architectures for particle filter based visual target tracking.
Proceedings of the 2011 International Green Computing Conference and Workshops, 2011

Non-uniform micro-channel design for stacked 3D-ICs.
Proceedings of the 48th Design Automation Conference, 2011

Cooling of 3D-IC using non-uniform micro-channels and sensor based dynamic thermal management.
Proceedings of the 49th Annual Allerton Conference on Communication, 2011

Energy-aware video coding of multiple views via workload balancing.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

Adaptable video compression and transmission using lossy and workload balancing techniques.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

Face Detection.
Proceedings of the Visual Analysis of Humans - Looking at People., 2011

2010
On-chip sensor-driven efficient thermal profile estimation algorithms.
ACM Trans. Design Autom. Electr. Syst., 2010

A Sparse Greedy Self-Adaptive Algorithm for Classification of Data.
Adv. Data Sci. Adapt. Anal., 2010

A statistical framework for designing on-chip thermal sensing infrastructure in nano-scale systems.
Proceedings of the 2010 International Symposium on Physical Design, 2010

Dynamic thermal management for single and multicore processors under soft thermal constraints.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Thermal and power-aware task scheduling for Hadoop based storage centric datacenters.
Proceedings of the International Green Computing Conference 2010, 2010

Adaptive and autonomous thermal tracking for high performance computing systems.
Proceedings of the 47th Design Automation Conference, 2010

2009
Adaptive Algorithm for Classifying Launch and Recovery of the HH-60H Seahawk.
J. Aerosp. Comput. Inf. Commun., 2009

Accurate temperature estimation using noisy thermal sensors.
Proceedings of the 46th Design Automation Conference, 2009

2008
Basic Algorithmic Techniques.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Variability Driven Gate Sizing for Binning Yield Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Algorithmic and Architectural Optimizations for Computationally Efficient Particle Filtering.
IEEE Trans. Image Process., 2008

Variability-Driven Formulation for Simultaneous Gate Sizing and Postsilicon Tunability Allocation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Chip level thermal profile estimation using on-chip temperature sensors.
Proceedings of the 26th International Conference on Computer Design, 2008

2007
A Quadratic Modeling-Based Framework for Accurate Statistical Timing Analysis Considering Correlations.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Leakage Control Through Fine-Grained Placement and Sizing of Sleep Transistors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Active mode leakage reduction using fine-grained forward body biasing strategy.
Integr., 2007

Efficient and Accurate Statistical Timing Analysis for Non-Linear Non-Gaussian Variability With Incremental Attributes.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Variability Driven Joint Leakage-Delay Optimization Through Gate Sizing with Provabale Convergence.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation.
Proceedings of the 2007 International Symposium on Physical Design, 2007

Statistical timing analysis using Kernel smoothing.
Proceedings of the 25th International Conference on Computer Design, 2007

Monte-Carlo driven stochastic optimization framework for handling fabrication variability.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

2006
Effective techniques for the generalized low-power binding problem.
ACM Trans. Design Autom. Electr. Syst., 2006

A statistical methodology for wire-length prediction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Probabilistic Evaluation of Solutions in Variability-Driven Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Probabilistic evaluation of solutions in variability-driven optimization.
Proceedings of the 2006 International Symposium on Physical Design, 2006

2005
Simultaneous V/sub t/ selection and assignment for leakage optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Power-driven simultaneous resource binding and floorplanning: a probabilistic approach.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Voltage scheduling under unpredictabilities: a risk management paradigm.
ACM Trans. Design Autom. Electr. Syst., 2005

On effective slack management in postscheduling phase.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Probabilistic dual-Vth leakage optimization under variability.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Algorithmic and Architectural Design Methodology for Particle Filters in Hardware.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Variability-Driven Buffer Insertion Considering Correlations.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

VLSI CAD tool protection by birthmarking design solutions.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

A general framework for accurate statistical timing analysis considering correlations.
Proceedings of the 42nd Design Automation Conference, 2005

Wake-up protocols for controlling current surges in MTCMOS-based technology.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Simultaneous floorplanning and resource binding: a probabilistic approach.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Timing driven gate duplication.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Empirical models for net-length probability distribution and applications.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Wire-length prediction using statistical techniques.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Efficient statistical timing analysis through error budgeting.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Variability inspired implementation selection problem.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

High level techniques for power-grid noise immunity.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

2003
Simultaneous Vt selection and assignment for leakage optimization.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Effective graph theoretic techniques for the generalized low power binding problem.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Achieving Design Closure Through Delay Relaxation Parameter.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

A Probabilistic Approach to Buffer Insertion.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

2002
Predictability in RT-Level Designs.
J. Circuits Syst. Comput., 2002

Budget Management with Applications.
Algorithmica, 2002

Predictability: Definition, Analysis and Optimization.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Early evaluation techniques for low power binding.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Predictability: definition, ananlysis and optimization.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

2001
On gate level power optimization using dual-supply voltages.
IEEE Trans. Very Large Scale Integr. Syst., 2001

On the complexity of gate duplication.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Activity-driven clock design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Design and analysis of physical design algorithms.
Proceedings of the 2001 International Symposium on Physical Design, 2001

Layout aware retiming.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

Timing driven gate duplication in technology independent phase.
Proceedings of ASP-DAC 2001, 2001

2000
Timing Driven Gate Duplication: Complexity Issues and Algorithms.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000


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