Prashant Dubey

According to our database, Prashant Dubey authored at least 10 papers between 2006 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2017

A 0.42V high bandwidth synthesizable parallel access smart memory fabric for computer vision.

Prashant Dubey, Kritika Aditya, Ankur Srivastava, Amit Khanuja, Jamil Kawa, Thu Nguyen

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2014

A 500 mV to 1.0 V 128 Kb SRAM in Sub 20 nm Bulk-FinFET Using Auto-adjustable Write Assist.

Prashant Dubey, Gaurav Ahuja, Vaibhav Verma, Sanjay Kumar Yadav, Amit Khanuja

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

2013

PODIA: Power Optimization through Differential Imbalanced Amplifier.

Prashant Dubey, Atul Kumar Kashyap, Navneet Gupta, Kaushik Saha

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

38dB Tuning Range Coupled VCO Based Divider Architecture with 68uW Power @2.0 GHz in 65nm CMOS.

Prashant Dubey, Rashmi Agarwal

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

2010

Study of Read Recovery Dynamic Faults in 6T SRAMS and Method to Improve Test Time.

Prashant Dubey, Akhil Garg, Shashank Mahajan

J. Electron. Test., 2010

2008

On Chip Jitter Measurement through a High Accuracy TDC.

Akhil Garg, Prashant Dubey

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007

Low Area Adaptive Fail-Data Compression Methodology for Defect Classification and Production Phase Prognosis.

Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

GALS Based Shared Test Architecture for Embedded Memories.

Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Built in Defect Prognosis for Embedded Memories.

Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006

Fuse Area Reduction Based on Quantitative Yield Analysis and Effective Chip Cost.

Akhil Garg, Prashant Dubey

Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006