Kermin Fleming

According to our database1, Kermin Fleming authored at least 27 papers between 2007 and 2017.

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Bibliography

2017
(FPL 2015) Scavenger: Automating the Construction of Application-Optimized Memory Hierarchies.
ACM Trans. Reconfigurable Technol. Syst., 2017

Custom Multicache Architectures for Heap Manipulating Programs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Automatic Construction of Program-Optimized FPGA Memory Networks.
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

2016
LMC: Automatic Resource-Aware Program-Optimized Memory Partitioning.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

A Study of Pointer-Chasing Performance on Shared-Memory Processor-FPGA Systems.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

The LEAP FPGA Operating System.
Proceedings of the FPGAs for Software Programmers, 2016

2015
Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures.
ACM Trans. Comput. Syst., 2015

Custom-sized caches in application-specific memory hierarchies.
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

Scavenger: Automating the construction of application-optimized memory hierarchies.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

MATCHUP: Memory Abstractions for Heap Manipulating Programs.
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

2014
The LEAP FPGA operating system.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Scalable multi-access flash store for big data analytics.
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

LEAP Shared Memories: Automating the Construction of FPGA Coherent Memories.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

2013
Scalable reconfigurable computing leveraging latency-insensitive channels.
PhD thesis, 2013

Optimizing under abstraction: Using prefetching to improve FPGA performance.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012
Spinal codes.
Proceedings of the ACM SIGCOMM 2012 Conference, 2012

ZIP-IO: Architecture for application-specific compression of Big Data.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Leveraging latency-insensitivity to ease multiple FPGA design.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

A hardware spinal decoder.
Proceedings of the Symposium on Architecture for Networking and Communications Systems, 2012

2011
Improving performance and lifetime of solid-state drives using hardware-accelerated compression.
IEEE Trans. Consumer Electron., 2011

WiLIS: Architectural modeling of wireless systems.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2011

Leap scratchpads: automatic memory and cache management for reconfigurable logic.
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2010
Airblue: a system for cross-layer wireless protocol development.
Proceedings of the 2010 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2010

2009
Implementing a fast cartesian-polar matrix interpolator.
Proceedings of the 7th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2009), 2009

2008
H.264 Decoder: A Case Study in Multiple Design Points.
Proceedings of the 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), 2008

High-throughput Pipelined Mergesort.
Proceedings of the 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), 2008

2007
Hardware Acceleration of Matrix Multiplication on a Xilinx FPGA.
Proceedings of the 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30, 2007


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