Anurag Negi

According to our database, Anurag Negi authored at least 15 papers between 2010 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2014

ZEBRA: Data-Centric Contention Management in Hardware Transactional Memory.

J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström

IEEE Trans. Parallel Distributed Syst., 2014

Performance and Energy Analysis of the Restricted Transactional Memory Implementation on Haswell.

Bhavishya Goel, J. Rubén Titos Gil, Anurag Negi, Sally A. McKee, Per Stenström

Proceedings of the 2014 IEEE 28th International Parallel and Distributed Processing Symposium, 2014

2013

Eager Beats Lazy: Improving Store Management in Eager Hardware Transactional Memory.

J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström

IEEE Trans. Parallel Distributed Syst., 2013

SCIN-cache: Fast speculative versioning in multithreaded cores.

Anurag Negi, J. Rubén Titos Gil

ACM Trans. Archit. Code Optim., 2013

Techniques to improve performance in requester-wins hardware transactional memory.

Adrià Armejach, J. Rubén Titos Gil, Anurag Negi, Osman S. Unsal, Adrián Cristal

ACM Trans. Archit. Code Optim., 2013

Efficient Forwarding of Producer-Consumer Data in Task-Based Programs.

Madhavan Manivannan, Anurag Negi, Per Stenström

Proceedings of the 42nd International Conference on Parallel Processing, 2013

HARP: Adaptive abort recurrence prediction for Hardware Transactional Memory.

Adrià Armejach, Anurag Negi, Adrián Cristal, Osman S. Unsal, Per Stenström, Tim Harris

Proceedings of the 20th Annual International Conference on High Performance Computing, 2013

2012

π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory.

Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström

Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

Transactional prefetching: narrowing the window of contention in hardware transactional memory.

Anurag Negi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Per Stenström

Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011

The Impact of Non-coherent Buffers on Lazy Hardware Transactional Memory Systems.

Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström

Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

ZEBRA: a data-centric, hybrid-policy hardware transactional memory design.

J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström

Proceedings of the 25th International Conference on Supercomputing, 2011, Tucson, AZ, USA, May 31, 2011

Eager Meets Lazy: The Impact of Write-Buffering on Hardware Transactional Memory.

Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström

Proceedings of the International Conference on Parallel Processing, 2011

Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory.

Anurag Negi, Per Stenström, J. Rubén Titos Gil, Manuel E. Acacio, José M. García

Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010

LV^*: A low complexity lazy versioning HTM infrastructure.

Anurag Negi, M. M. Waliullah, Per Stenström

Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

LV*: a class of lazy versioning HTMs for low-cost integration of transactional memory systems.

Anurag Negi, M. M. Waliullah, Per Stenström

Proceedings of the Second International Forum on Next-Generation Multicore/Manycore Technologies, 2010