Madhavan Manivannan

According to our database, Madhavan Manivannan authored at least 29 papers between 2007 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

Approx-RM: Reducing Energy on Heterogeneous Multicore Processors under Accuracy and Timing Constraints.

Muhammad Waqar Azhar, Madhavan Manivannan, Per Stenström

ACM Trans. Archit. Code Optim., September, 2023

JOSS: Joint Exploration of CPU-Memory DVFS and Task Scheduling for Energy Efficiency.

Jing Chen, Madhavan Manivannan, Bhavishya Goel, Miquel Pericàs

Proceedings of the 52nd International Conference on Parallel Processing, 2023

SCALE: Secure and Scalable Cache Partitioning.

Nadja Ramhöj Holtryd, Madhavan Manivannan, Per Stenström

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2023

SoK: Analysis of Root Causes and Defense Strategies for Attacks on Microarchitectural Optimizations.

Nadja Ramhöj Holtryd, Madhavan Manivannan, Per Stenström

Proceedings of the 8th IEEE European Symposium on Security and Privacy, 2023

eProcessor: European, Extendable, Energy-Efficient, Extreme-Scale, Extensible, Processor Ecosystem.

Lluc Alvarez, Abraham Ruiz, Arnau Bigas-Soldevilla, Pavel Kuroedov, Alberto González, Hamsika Mahale, Noe Bustamante, Albert Aguilera, Francesco Minervini, Javier Salamero, Oscar Palomar, Vassilis Papaefstathiou, Antonis Psathakis, Nikolaos Dimou, Michalis Giaourtas, Iasonas Mastorakis, Georgios Ieronymakis, Georgios-Michail Matzouranis, Vassilis Flouris, Nick Kossifidis, Manolis Marazakis, Bhavishya Goel, Madhavan Manivannan, Ahsen Ejaz, Panagiotis Strikos, Mateo Vázquez, Ioannis Sourdis, Pedro Trancoso, Per Stenström, Jens Hagemeyer, Lennart Tigges, Nils Kucza, Jean-Marc Philippe, Ioannis Papaefstathiou

Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023

2022

Cooperative Slack Management: Saving Energy of Multicore Processors by Trading Performance Slack Between QoS-Constrained Applications.

Mehrzad Nejat, Madhavan Manivannan, Miquel Pericàs, Per Stenström

ACM Trans. Archit. Code Optim., 2022

ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes.

Jing Chen, Madhavan Manivannan, Mustafa Abduljabbar, Miquel Pericàs

ACM Trans. Archit. Code Optim., 2022

STEER: Asymmetry-aware Energy Efficient Task Scheduler for Cluster-based Multicore Architectures.

Jing Chen, Madhavan Manivannan, Bhavishya Goel, Mustafa Abduljabbar, Miquel Pericàs

Proceedings of the 2022 IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2022

2021

CBP: Coordinated management of cache partitioning, bandwidth partitioning and prefetch throttling.

Nadja Ramhöj Holtryd, Madhavan Manivannan, Per Stenström, Miquel Pericàs

Proceedings of the 30th International Conference on Parallel Architectures and Compilation Techniques, 2021

2020

Coordinated management of DVFS and cache partitioning under QoS constraints to save energy in multi-core systems.

Mehrzad Nejat, Madhavan Manivannan, Miquel Pericàs, Per Stenström

J. Parallel Distributed Comput., 2020

Coordinated Management of Processor Configuration and Cache Partitioning to Optimize Energy under QoS Constraints.

Mehrzad Nejat, Madhavan Manivannan, Miquel Pericàs, Per Stenström

Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2020

DELTA: Distributed Locality-Aware Cache Partitioning for Tile-based Chip Multiprocessors.

Nadja Holtryd, Madhavan Manivannan, Per Stenström, Miquel Pericàs

Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS), 2020

Scheduling Task-parallel Applications in Dynamically Asymmetric Environments.

Jing Chen, Pirah Noor Soomro, Mustafa Abduljabbar, Madhavan Manivannan, Miquel Pericàs

Proceedings of the ICPP Workshops '20: Workshops, Edmonton, AB, Canada, August 17-20, 2020, 2020

Enhancing Multithreaded Performance of Asymmetric Multicores with SIMD Offloading.

Jeckson Dellagostin Souza, Madhavan Manivannan, Miquel Pericàs, Antonio Carlos Schneider Beck

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing.

Behzad Salami, Konstantinos Parasyris, Adrián Cristal, Osman S. Unsal, Xavier Martorell, Paul Carpenter, Raúl de la Cruz, Leonardo Bautista-Gomez, Daniel A. Jiménez, Carlos Álvarez, Seyed Saber Nabavi Larimi, Sergi Madonar, Miquel Pericàs, Pedro Trancoso, Mustafa Abduljabbar, Jing Chen, Pirah Noor Soomro, Madhavan Manivannan, Micha vor dem Berge, Stefan Krupop, Frank Klawonn, Al Mekhlafi, Sigrun May, Tobias Becker, Georgi Gaydadjiev, Hans Salomonsson, Devdatt P. Dubhashi, Oron Port, Yoav Etsion, Do Le Quoc, Christof Fetzer, Martin Kaiser, Nils Kucza, Jens Hagemeyer, René Griessl, Lennart Tigges, Kevin Mika, A. Hüffmeier, Marcelo Pasin, Valerio Schiavoni, Isabelly Rocha, Christian Göttel, Pascal Felber

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Enhancing Thread-Level Parallelism in Asymmetric Multicores using Transparent Instruction Offloading.

Jeckson Dellagostin Souza, Madhavan Manivannan, Miquel Pericàs, Antonio Carlos Schneider Beck

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing.

Behzad Salami, Konstantinos Parasyris, Adrián Cristal, Osman S. Unsal, Xavier Martorell, Paul Carpenter, Raúl de la Cruz, Leonardo Bautista-Gomez, Daniel A. Jiménez, Carlos Álvarez, S. Nabavi, Sergi Madonar, Miquel Pericàs, Pedro Trancoso, Mustafa Abduljabbar, Jing Chen, Pirah Noor Soomro, Madhavan Manivannan, Micha vor dem Berge, Stefan Krupop, Frank Klawonn, Al Mekhlafi, Sigrun May, Tobias Becker, Georgi Gaydadjiev, Daniel Ödman, Hans Salomonsson, Devdatt P. Dubhashi, Oron Port, Yoav Etsion, Do Le Quoc, Christof Fetzer, Martin Kaiser, Nils Kucza, Jens Hagemeyer, René Griessl, Lennart Tigges, Kevin Mika, A. Hüffmeier, Th. Jungeblu, Marcelo Pasin, Valerio Schiavoni, Isabelly Rocha, Christian Göttel, Pascal Felber

CoRR, 2019

2018

Global Dead-Block Management for Task-Parallel Programs.

Madhavan Manivannan, Miquel Pericàs, Vassilis Papaefstathiou, Per Stenström

ACM Trans. Archit. Code Optim., 2018

2017

Runtime-Assisted Global Cache Management for Task-Based Parallel Programs.

Madhavan Manivannan, Miquel Pericàs, Vassilis Papaefstathiou, Per Stenström

IEEE Comput. Archit. Lett., 2017

2016

Towards Runtime-Assisted Cache Management for Task-Parallel Programs.

Madhavan Manivannan

PhD thesis, 2016

RADAR: Runtime-assisted dead region management for last-level caches.

Madhavan Manivannan, Vassilis Papaefstathiou, Miquel Pericàs, Per Stenström

Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

2014

Runtime-Guided Cache Coherence Optimizations in Multi-core Architectures.

Madhavan Manivannan, Per Stenström

Proceedings of the 2014 IEEE 28th International Parallel and Distributed Processing Symposium, 2014

2013

Efficient Forwarding of Producer-Consumer Data in Task-Based Programs.

Madhavan Manivannan, Anurag Negi, Per Stenström

Proceedings of the 42nd International Conference on Parallel Processing, 2013

2011

Poster: implications of merging phases on scalability of multi-core architectures.

Madhavan Manivannan, Ben H. H. Juurlink, Per Stenström

Proceedings of the 25th International Conference on Supercomputing, 2011, Tucson, AZ, USA, May 31, 2011

Implications of Merging Phases on Scalability of Multi-core Architectures.

Madhavan Manivannan, Ben H. H. Juurlink, Per Stenström

Proceedings of the International Conference on Parallel Processing, 2011

2009

Towards modeling and integrated design automation of supercomputing clusters (MIDAS).

Nagarajan Venkateswaran, Aravind Vasudevan, Balaji Subramaniam, Ravindhiran Mukundrajan, T. P. Ramnath Sai Sagar, Madhavan Manivannan, Sriram Murali, Vinoth Krishnan Elangovan

Comput. Sci. Res. Dev., 2009

2008

On the concept of simultaneous execution of multiple applications on hierarchically based cluster and the silicon operating system.

Nagarajan Venkateswaran, Vinoth Krishnan Elangovan, Karthik Ganesan, T. R. S. Sagar, S. Aananthakrishanan, S. Ramalingam, Shyamsundar Gopalakrishnan, Madhavan Manivannan, Deepak Srinivasan, Viswanath Krishnamurthy, Karthik Chandrasekar, Viswanath Venkatesan, Balaji Subramaniam, V. Sangkar, Aravind Vasudevan, Shrikanth Ganapathy, Sriram Murali, M. Thyagarajan

Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

2007

Future generation supercomputers II: a paradigm for cluster architecture.

Nagarajan Venkateswaran, Deepak Srinivasan, Madhavan Manivannan, T. P. Ramnath Sai Sagar, Shyamsundar Gopalakrishnan, Vinoth Krishnan Elangovan, Arvind M, Prem Kumar Ramesh, Karthik Ganesan, Viswanath Krishnamurthy, Sivaramakrishnan

SIGARCH Comput. Archit. News, 2007

Future generation supercomputers I: a paradigm for node architecture.

Nagarajan Venkateswaran, Deepak Srinivasan, Madhavan Manivannan, T. P. Ramnath Sai Sagar, Shyamsundar Gopalakrishnan, Vinoth Krishnan Elangovan, Karthik Chandrasekar, Prem Kumar Ramesh, Viswanath Venkatesan, Arvindakshan Babu, Sudharshan

SIGARCH Comput. Archit. News, 2007