Manuel E. Acacio
Orcid: 0000-0003-0935-4078Affiliations:
- University of Murcia, Spain
According to our database1,
Manuel E. Acacio
authored at least 120 papers
between 1999 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
Microprocess. Microsystems, 2024
2023
STIFT: A Spatio-Temporal Integrated Folding Tree for Efficient Reductions in Flexible DNN Accelerators.
ACM J. Emerg. Technol. Comput. Syst., October, 2023
J. Parallel Distributed Comput., March, 2023
Flexagon: A Multi-dataflow Sparse-Sparse Matrix Multiplication Accelerator for Efficient DNN Processing.
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023
Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques, 2023
2022
DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memory.
IEEE Trans. Parallel Distributed Syst., 2022
J. Supercomput., 2022
Proceedings of the 30th Euromicro International Conference on Parallel, 2022
Understanding the Design-Space of Sparse/Dense Multiphase GNN dataflows on Spatial Accelerators.
Proceedings of the 2022 IEEE International Parallel and Distributed Processing Symposium, 2022
2021
CoRR, 2021
STONNE: Enabling Cycle-Level Microarchitectural Simulation for DNN Inference Accelerators.
IEEE Comput. Archit. Lett., 2021
A novel network fabric for efficient spatio-temporal reduction in flexible DNN accelerators.
Proceedings of the NOCS '21: International Symposium on Networks-on-Chip, 2021
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
2020
IEEE Trans. Parallel Distributed Syst., 2020
Ant Colony Optimization-Based Streaming Feature Selection: An Application to the Medical Image Diagnosis.
Sci. Program., 2020
J. Parallel Distributed Comput., 2020
CoRR, 2020
2019
IEEE Trans. Parallel Distributed Syst., 2019
Future Gener. Comput. Syst., 2019
Foreword to the Special Issue on Processors, Interconnects, Storage, and Caches for Exascale Systems.
Concurr. Comput. Pract. Exp., 2019
Proceedings of the Euro-Par 2019: Parallel Processing Workshops, 2019
2018
Parallel implementations of the 3D fast wavelet transform on a Raspberry Pi 2 cluster.
J. Supercomput., 2018
Sci. Program., 2018
J. Parallel Distributed Comput., 2018
SAWS: Simple and Adaptive Warp Scheduling for Improved Performance in Throughput Processors.
Proceedings of the 26th Euromicro International Conference on Parallel, 2018
2017
To be silent or not: on the impact of evictions of clean data in cache-coherent multicores.
J. Supercomput., 2017
Concurr. Comput. Pract. Exp., 2017
Proceedings of the International Conference on Supercomputing, 2017
2016
Are distributed sharing codes a solution to the scalability problem of coherence directories in manycores? An evaluation study.
J. Supercomput., 2016
Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016
2015
Proceedings of the Handbook on Data Centers, 2015
Proceedings of the Handbook on Data Centers, 2015
J. Supercomput., 2015
J. Supercomput., 2015
IEEE Trans. Computers, 2015
Proceedings of the 11th IEEE International Conference on e-Science, 2015
2014
IEEE Trans. Parallel Distributed Syst., 2014
Selective dynamic serialization for reducing energy consumption in hardware transactional memory systems.
J. Supercomput., 2014
Characterization of a List-Based Directory Cache Coherence Protocol for Manycore CMPs.
Proceedings of the Euro-Par 2014: Parallel Processing Workshops, 2014
2013
IEEE Trans. Parallel Distributed Syst., 2013
IEEE Trans. Parallel Distributed Syst., 2013
Design of an efficient communication infrastructure for highly contended locks in many-core CMPs.
J. Parallel Distributed Comput., 2013
Concurr. Comput. Pract. Exp., 2013
ECONO: Express coherence notifications for efficient cache coherency in many-core CMPs.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013
Proceedings of the International Conference on Computational Science, 2013
Proceedings of the Euro-Par 2013 Parallel Processing, 2013
Deploying Hardware Locks to Improve Performance and Energy Efficiency of Hardware Transactional Memory.
Proceedings of the Architecture of Computing Systems - ARCS 2013, 2013
2012
IEEE Trans. Parallel Distributed Syst., 2012
Stencil computations on heterogeneous platforms for the Jacobi method: GPUs versus Cell BE.
J. Supercomput., 2012
ACM Trans. Archit. Code Optim., 2012
Using Heterogeneous Networks to Improve Energy Efficiency in Direct Coherence Protocols for Many-Core CMPs.
Proceedings of the IEEE 24th International Symposium on Computer Architecture and High Performance Computing, 2012
Dynamic Serialization: Improving Energy Consumption in Eager-Eager Hardware Transactional Memory Systems.
Proceedings of the 20th Euromicro International Conference on Parallel, 2012
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
An Experience of Early Initiation to Parallelism in the Computing Engineering Degree at the University of Murcia, Spain.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012
Dynamic Last-Level Cache Allocation to Reduce Area and Power Overhead in Directory Coherence Protocols.
Proceedings of the Euro-Par 2012 Parallel Processing - 18th International Conference, 2012
Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCs.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
Proceedings of the 25th International Conference on Supercomputing, 2011, Tucson, AZ, USA, May 31, 2011
Proceedings of the International Conference on Parallel Processing, 2011
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011
2010
IEEE Trans. Parallel Distributed Syst., 2010
Dealing with Transient Faults in the Interconnection Network of CMPs at the Cache Coherence Level.
IEEE Trans. Parallel Distributed Syst., 2010
Characterizing the basic synchronization and communication operations in Dual Cell-based Blades through CellStats.
J. Supercomput., 2010
IEEE Trans. Computers, 2010
Exploiting address compression and heterogeneous interconnects for efficient message management in tiled CMPs.
J. Syst. Archit., 2010
Proceedings of the 22st International Symposium on Computer Architecture and High Performance Computing, 2010
Proceedings of the 18th Euromicro Conference on Parallel, 2010
A G-Line-Based Network for Fast and Efficient Barrier Synchronization in Many-Core CMPs.
Proceedings of the 39th International Conference on Parallel Processing, 2010
Proceedings of the 2010 International Conference on High Performance Computing, 2010
Proceedings of the Euro-Par 2010 Parallel Processing Workshops, 2010
Proceedings of the 7th Conference on Computing Frontiers, 2010
2009
Proceedings of the 17th Euromicro International Conference on Parallel, 2009
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009
Proceedings of the 16th International Conference on High Performance Computing, 2009
Fast and Efficient Synchronization and Communication Collective Primitives for Dual Cell-Based Blades.
Proceedings of the Euro-Par 2009 Parallel Processing, 2009
Dealing with Traffic-Area Trade-Off in Direct Coherence Protocols for Many-Core CMPs.
Proceedings of the Advanced Parallel Processing Technologies, 8th International Symposium, 2009
2008
Extending the TokenCMP Cache Coherence Protocol for Low Overhead Fault Tolerance in CMP Architectures.
IEEE Trans. Parallel Distributed Syst., 2008
An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures.
J. Supercomput., 2008
Two proposals for the inclusion of directory information in the last-level private caches of glueless shared-memory multiprocessors.
J. Parallel Distributed Comput., 2008
Proceedings of the 16th Euromicro International Conference on Parallel, 2008
CellStats: A Tool to Evaluate the Basic Synchronization and Communication Operations of the Cell BE.
Proceedings of the 16th Euromicro International Conference on Parallel, 2008
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008
Address Compression and Heterogeneous Interconnects for Energy-Efficient High-Performance in Tiled CMPs.
Proceedings of the 2008 International Conference on Parallel Processing, 2008
Characterizing the Basic Synchronization and Communication Operations in Dual Cell-Based Blades.
Proceedings of the Computational Science, 2008
Proceedings of the High Performance Computing, 2008
Proceedings of the High Performance Computing, 2008
Proceedings of the 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2008
Multicore Platforms for Scientific Computing: Cell BE and NVIDIA Tesla.
Proceedings of the 2008 International Conference on Scientific Computing, 2008
Scalable Directory Organization for Tiled CMP Architectures.
Proceedings of the 2008 International Conference on Computer Design, 2008
2007
An efficient implementation of a 3D wavelet transform based encoder on hyper-threading technology.
Parallel Comput., 2007
Proceedings of the 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 2007
Direct Coherence: Bringing Together Performance and Scalability in Shared-Memory Multiprocessors.
Proceedings of the High Performance Computing, 2007
Efficient Message Management in Tiled CMP Architectures Using a Heterogeneous Interconnection Network.
Proceedings of the High Performance Computing, 2007
Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures.
Proceedings of the 21st International Conference on Advanced Information Networking and Applications (AINA 2007), 2007
2006
Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006
Proceedings of the Third Conference on Computing Frontiers, 2006
2005
IEEE Trans. Parallel Distributed Syst., 2005
J. Syst. Archit., 2005
Proceedings of the 13th Euromicro Workshop on Parallel, 2005
Memory Subsystem Characterization in a 16-Core Snoop-Based Chip-Multiprocessor Architecture.
Proceedings of the High Performance Computing and Communications, 2005
A Novel Lightweight Directory Architecture for Scalable Shared-Memory Multiprocessors.
Proceedings of the Euro-Par 2005, Parallel Processing, 11th International Euro-Par Conference, Lisbon, Portugal, August 30, 2005
2004
An Architecture for High-Performance Scalable Shared-Memory Multiprocessors Exploiting On-Chip Integration.
IEEE Trans. Parallel Distributed Syst., 2004
Proceedings of the Computational Science, 2004
2002
MPI-Delphi: an MPI implementation for visual programming environments and heterogeneous computing.
Future Gener. Comput. Syst., 2002
Owner prediction for accelerating cache-to-cache transfer misses in a cc-NUMA architecture.
Proceedings of the 2002 ACM/IEEE conference on Supercomputing, 2002
Reducing the Latency of L2 Misses in Shared-Memory Multiprocessors through On-Chip Directory Integration.
Proceedings of the 10th Euromicro Workshop on Parallel, 2002
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 2002
2001
Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001
1999
The Parallel EM Algorithm and its Applications in Computer Vision.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999
The MPI-Delphi Interface: A Visual Programming Environment for Clusters of Workstations.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999
A Performance Evaluation of P-EDR in Different Parallel Environments.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999
P-EDR: An Algorithm for Parallel Implementation of Parzen Density Estimation from Uncertain Observations.
Proceedings of the 13th International Parallel Processing Symposium / 10th Symposium on Parallel and Distributed Processing (IPPS / SPDP '99), 1999
Proceedings of the Parallel Computation, 1999