J. Rubén Titos Gil

According to our database, J. Rubén Titos Gil authored at least 30 papers between 2008 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2020

Concurrent Irrevocability in Best-Effort Hardware Transactional Memory.

J. Rubén Titos Gil, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio

IEEE Trans. Parallel Distributed Syst., 2020

PfTouch: Concurrent page-fault handling for Intel restricted transactional memory.

J. Rubén Titos Gil, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio

J. Parallel Distributed Comput., 2020

2019

Way Combination for an Adaptive and Scalable Coherence Directory.

J. Rubén Titos Gil, Antonio Flores, Ricardo Fernández Pascual, Alberto Ros, Salvador Petit, Julio Sahuquillo, Manuel E. Acacio

IEEE Trans. Parallel Distributed Syst., 2019

2017

Way-combining directory: an adaptive and scalable low-cost coherence directory.

J. Rubén Titos Gil, Antonio Flores, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio

Proceedings of the International Conference on Supercomputing, 2017

2016

Architectural support for efficient message passing on shared memory multi-cores.

J. Rubén Titos Gil, Oscar Palomar, Osman S. Unsal, Adrián Cristal

J. Parallel Distributed Comput., 2016

Energy minimization at all layers of the data center: The ParaDIME project.

Oscar Palomar, Santhosh Kumar Rethinagiri, Gulay Yalcin, J. Rubén Titos Gil, Pablo Prieto, Emma Torrella, Osman S. Unsal, Adrián Cristal, Pascal Felber, Anita Sobe, Yaroslav Hayduk, Mascha Kurpicz, Christof Fetzer, Thomas Knauth, Malte Schneegaß, Jens Struckmeier, Dragomir Milojevic

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

Hardware Approaches to Transactional Memory in Chip Multiprocessors.

J. Rubén Titos Gil, Manuel E. Acacio

Proceedings of the Handbook on Data Centers, 2015

ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy for data centers.

Santhosh Kumar Rethinagiri, Oscar Palomar, Anita Sobe, Gulay Yalcin, Thomas Knauth, J. Rubén Titos Gil, Pablo Prieto, Malte Schneegaß, Adrián Cristal, Osman S. Unsal, Pascal Felber, Christof Fetzer, Dragomir Milojevic

Microprocess. Microsystems, 2015

Enhancing Garbage Collection Synchronization Using Explicit Bit Barriers.

Jochen Hollmann, J. Rubén Titos Gil, Per Stenström

Proceedings of the 44th International Conference on Parallel Processing, 2015

DiMP: Architectural Support for Direct Message Passing on Shared Memory Multi-cores.

J. Rubén Titos Gil, Oscar Palomar, Osman S. Unsal, Adrián Cristal

Proceedings of the 44th International Conference on Parallel Processing, 2015

2014

ZEBRA: Data-Centric Contention Management in Hardware Transactional Memory.

J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström

IEEE Trans. Parallel Distributed Syst., 2014

Selective dynamic serialization for reducing energy consumption in hardware transactional memory systems.

Epifanio Gaona-Ramírez, J. Rubén Titos Gil, Juan Fernández, Manuel E. Acacio

J. Supercomput., 2014

Performance and Energy Analysis of the Restricted Transactional Memory Implementation on Haswell.

Bhavishya Goel, J. Rubén Titos Gil, Anurag Negi, Sally A. McKee, Per Stenström

Proceedings of the 2014 IEEE 28th International Parallel and Distributed Processing Symposium, 2014

2013

Eager Beats Lazy: Improving Store Management in Eager Hardware Transactional Memory.

J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström

IEEE Trans. Parallel Distributed Syst., 2013

Efficient Eager Management of Conflicts for Scalable Hardware Transactional Memory.

J. Rubén Titos Gil, Manuel E. Acacio, José M. García

IEEE Trans. Parallel Distributed Syst., 2013

SCIN-cache: Fast speculative versioning in multithreaded cores.

Anurag Negi, J. Rubén Titos Gil

ACM Trans. Archit. Code Optim., 2013

Techniques to improve performance in requester-wins hardware transactional memory.

Adrià Armejach, J. Rubén Titos Gil, Anurag Negi, Osman S. Unsal, Adrián Cristal

ACM Trans. Archit. Code Optim., 2013

On the design of energy-efficient hardware transactional memory systems.

Epifanio Gaona-Ramírez, J. Rubén Titos Gil, Juan Fernández, Manuel E. Acacio

Concurr. Comput. Pract. Exp., 2013

2012

Hardware transactional memory with software-defined conflicts.

J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Tim Harris, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero

ACM Trans. Archit. Code Optim., 2012

Dynamic Serialization: Improving Energy Consumption in Eager-Eager Hardware Transactional Memory Systems.

Epifanio Gaona-Ramírez, J. Rubén Titos Gil, Manuel E. Acacio, Juan Fernández

Proceedings of the 20th Euromicro International Conference on Parallel, 2012

π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory.

Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström

Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

2011

The Impact of Non-coherent Buffers on Lazy Hardware Transactional Memory Systems.

Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström

Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

ZEBRA: a data-centric, hybrid-policy hardware transactional memory design.

J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström

Proceedings of the 25th International Conference on Supercomputing, 2011, Tucson, AZ, USA, May 31, 2011

Eager Meets Lazy: The Impact of Write-Buffering on Hardware Transactional Memory.

Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström

Proceedings of the International Conference on Parallel Processing, 2011

Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory.

Anurag Negi, Per Stenström, J. Rubén Titos Gil, Manuel E. Acacio, José M. García

Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory.

Adrià Armejach, Azam Seyedi, J. Rubén Titos Gil, Ibrahim Hur, Adrián Cristal, Osman S. Unsal, Mateo Valero

Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010

Characterizing Energy Consumption in Hardware Transactional Memory Systems.

Epifanio Gaona-Ramírez, J. Rubén Titos Gil, Juan Fernández, Manuel E. Acacio

Proceedings of the 22st International Symposium on Computer Architecture and High Performance Computing, 2010

2009

Speculation-based conflict resolution in hardware transactional memory.

J. Rubén Titos Gil, Manuel E. Acacio, José Manuel García Carrasco

Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

2008

Characterization of Conflicts in Log-Based Transactional Memory (LogTM).

J. Rubén Titos Gil, Manuel E. Acacio, José Manuel García Carrasco

Proceedings of the 16th Euromicro International Conference on Parallel, 2008

Directory-Based Conflict Detection in Hardware Transactional Memory.

J. Rubén Titos Gil, Manuel E. Acacio, José M. García

Proceedings of the High Performance Computing, 2008