J. Rubén Titos Gil
According to our database1,
J. Rubén Titos Gil
authored at least 27 papers
between 2008 and 2017.
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Bibliography
2017
Way-combining directory: an adaptive and scalable low-cost coherence directory.
Proceedings of the International Conference on Supercomputing, 2017
2016
Architectural support for efficient message passing on shared memory multi-cores.
J. Parallel Distrib. Comput., 2016
Energy minimization at all layers of the data center: The ParaDIME project.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
Hardware Approaches to Transactional Memory in Chip Multiprocessors.
Proceedings of the Handbook on Data Centers, 2015
ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy for data centers.
Microprocessors and Microsystems - Embedded Hardware Design, 2015
Enhancing Garbage Collection Synchronization Using Explicit Bit Barriers.
Proceedings of the 44th International Conference on Parallel Processing, 2015
DiMP: Architectural Support for Direct Message Passing on Shared Memory Multi-cores.
Proceedings of the 44th International Conference on Parallel Processing, 2015
2014
ZEBRA: Data-Centric Contention Management in Hardware Transactional Memory.
IEEE Trans. Parallel Distrib. Syst., 2014
Selective dynamic serialization for reducing energy consumption in hardware transactional memory systems.
The Journal of Supercomputing, 2014
Performance and Energy Analysis of the Restricted Transactional Memory Implementation on Haswell.
Proceedings of the 2014 IEEE 28th International Parallel and Distributed Processing Symposium, 2014
2013
Eager Beats Lazy: Improving Store Management in Eager Hardware Transactional Memory.
IEEE Trans. Parallel Distrib. Syst., 2013
Efficient Eager Management of Conflicts for Scalable Hardware Transactional Memory.
IEEE Trans. Parallel Distrib. Syst., 2013
SCIN-cache: Fast speculative versioning in multithreaded cores.
TACO, 2013
Techniques to improve performance in requester-wins hardware transactional memory.
TACO, 2013
On the design of energy-efficient hardware transactional memory systems.
Concurrency and Computation: Practice and Experience, 2013
2012
Hardware transactional memory with software-defined conflicts.
TACO, 2012
Dynamic Serialization: Improving Energy Consumption in Eager-Eager Hardware Transactional Memory Systems.
Proceedings of the 20th Euromicro International Conference on Parallel, 2012
π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012
2011
The Impact of Non-coherent Buffers on Lazy Hardware Transactional Memory Systems.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
ZEBRA: a data-centric, hybrid-policy hardware transactional memory design.
Proceedings of the 25th International Conference on Supercomputing, 2011, Tucson, AZ, USA, May 31, 2011
Eager Meets Lazy: The Impact of Write-Buffering on Hardware Transactional Memory.
Proceedings of the International Conference on Parallel Processing, 2011
Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011
Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011
2010
Characterizing Energy Consumption in Hardware Transactional Memory Systems.
Proceedings of the 22st International Symposium on Computer Architecture and High Performance Computing, 2010
2009
Speculation-based conflict resolution in hardware transactional memory.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009
2008
Characterization of Conflicts in Log-Based Transactional Memory (LogTM).
Proceedings of the 16th Euromicro International Conference on Parallel, 2008
Directory-Based Conflict Detection in Hardware Transactional Memory.
Proceedings of the High Performance Computing, 2008