Arash Reyhani-Masoleh
Orcid: 0000-0001-9743-6975
According to our database1,
Arash Reyhani-Masoleh
authored at least 65 papers
between 2000 and 2022.
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Bibliography
2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
2021
Proceedings of the 28th IEEE Symposium on Computer Arithmetic, 2021
2020
IEEE Trans. Computers, 2020
2019
IEEE Trans. Computers, 2019
2018
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018
Improving performance of FPGA-based SR-latch PUF using Transient Effect Ring Oscillator and programmable delay lines.
Integr., 2018
Proceedings of the 25th IEEE Symposium on Computer Arithmetic, 2018
2017
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017
A New Multiplicative Inverse Architecture in Normal Basis Using Novel Concurrent Serial Squaring and Multiplication.
Proceedings of the 24th IEEE Symposium on Computer Arithmetic, 2017
2016
Multiple-Bit Parity-Based Concurrent Fault Detection Architecture for Parallel CRC Computation.
IEEE Trans. Computers, 2016
New Architectures for Digit-Level Single, Hybrid-Double, Hybrid-Triple Field Multiplications and Exponentiation Using Gaussian Normal Bases.
IEEE Trans. Computers, 2016
High-Speed Hybrid-Double Multiplication Architectures Using New Serial-Out Bit-Level Mastrovito Multipliers.
IEEE Trans. Computers, 2016
Keymill: Side-Channel Resilient Key Generator, A New Concept for SCA-Security by Design - A New Concept for SCA-Security by Design.
Proceedings of the Selected Areas in Cryptography - SAC 2016, 2016
Proceedings of the 23nd IEEE Symposium on Computer Arithmetic, 2016
2015
Parallel and High-Speed Computations of Elliptic Curve Cryptography Using Hybrid-Double Multipliers.
IEEE Trans. Parallel Distributed Syst., 2015
Comments on "Low-Latency Digit-Serial Systolic Double Basis Multiplier over GF(2<sup>m</sup>) Using Subquadratic Toeplitz Matrix-Vector Product Approach".
IEEE Trans. Computers, 2015
New Hardware Implementations of WG(29, 11) and WG-16 Stream Ciphers Using Polynomial Basis.
IEEE Trans. Computers, 2015
New Regular Radix-8 Scheme for Elliptic Curve Scalar Multiplication without Pre-Computation.
IEEE Trans. Computers, 2015
Proceedings of the 22nd IEEE Symposium on Computer Arithmetic, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
Efficient and Concurrent Reliable Realization of the Secure Cryptographic SHA-3 Algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
2013
IEEE Trans. Circuits Syst. II Express Briefs, 2013
Low-Complexity Multiplier Architectures for Single and Hybrid-Double Multiplications in Gaussian Normal Bases.
IEEE Trans. Computers, 2013
2012
On Countermeasures Against Fault Attacks on Elliptic Curve Cryptography Using Fault Detection.
Proceedings of the Fault Analysis in Cryptography, 2012
Efficient FPGA Implementations of Point Multiplication on Binary Edwards and Generalized Hessian Curves Using Gaussian Normal Basis.
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Trans. Computers, 2012
2011
A Lightweight High-Performance Fault Detection Scheme for the Advanced Encryption Standard Using Composite Fields.
IEEE Trans. Very Large Scale Integr. Syst., 2011
Digit-Level Semi-Systolic and Systolic Structures for the Shifted Polynomial Basis Multiplication Over Binary Extension Fields.
IEEE Trans. Very Large Scale Integr. Syst., 2011
A Low-Power High-Performance Concurrent Fault Detection Approach for the Composite Field S-Box and Inverse S-Box.
IEEE Trans. Computers, 2011
Concurrent Error Detection in Montgomery Multiplication over Binary Extension Fields.
IEEE Trans. Computers, 2011
A Fault Detection Scheme for the FPGA Implementation of SHA-1 and SHA-512 Round Computations.
J. Electron. Test., 2011
Secure Clustering and Symmetric Key Establishment in Heterogeneous Wireless Sensor Networks.
EURASIP J. Wirel. Commun. Netw., 2011
A High-Performance Fault Diagnosis Approach for the AES SubBytes Utilizing Mixed Bases.
Proceedings of the 2011 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2011
Reliable Hardware Architectures for the Third-Round SHA-3 Finalist Grostl Benchmarked on FPGA Platform.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
2010
Concurrent Structure-Independent Fault Detection Schemes for the Advanced Encryption Standard.
IEEE Trans. Computers, 2010
Proceedings of the Arithmetic of Finite Fields, Third International Workshop, 2010
2009
IEEE Trans. Computers, 2009
Fault Detection Structures of the S-boxes and the Inverse S-boxes for the Advanced Encryption Standard.
J. Electron. Test., 2009
Proceedings of the 2009 IEEE International Conference on Electro/Information Technology, 2009
Proceedings of the 2009 IEEE International Conference on Electro/Information Technology, 2009
2008
Digit-Serial Structures for the Shifted Polynomial Basis Multiplication over Binary Extension Fields.
Proceedings of the Arithmetic of Finite Fields, 2nd International Workshop, 2008
Proceedings of the 2008 IEEE/IPIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), 2008
Proceedings of the 2008 IEEE/IPIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), 2008
Proceedings of the Cryptographic Hardware and Embedded Systems, 2008
A Lightweight Concurrent Fault Detection Scheme for the AES S-Boxes Using Normal Basis.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2008
Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers, 2008
2007
A Structure-independent Approach for Fault Detection Hardware Implementations of the Advanced Encryption Standard.
Proceedings of the Fourth International Workshop on Fault Diagnosis and Tolerance in Cryptography, 2007
Fault Detection Structures for the Montgomery Multiplication over Binary Extension Fields.
Proceedings of the Fourth International Workshop on Fault Diagnosis and Tolerance in Cryptography, 2007
2006
IEEE Trans. Computers, 2006
Efficient Algorithms and Architectures for Field Multiplication Using Gaussian Normal Bases.
IEEE Trans. Computers, 2006
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006
2005
IEEE Trans. Computers, 2005
2004
ACM Trans. Embed. Comput. Syst., 2004
ACM Trans. Embed. Comput. Syst., 2004
Low Complexity Bit Parallel Architectures for Polynomial Basis Multiplication over GF(2^{m}).
IEEE Trans. Computers, 2004
2003
IEEE Trans. Computers, 2003
Proceedings of the Cryptographic Hardware and Embedded Systems, 2003
Proceedings of the 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 2003
2002
A New Construction of Massey-Omura Parallel Multiplier over <i>GF</i>(2<sup><i>m</i></sup>).
IEEE Trans. Computers, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the Cryptographic Hardware and Embedded Systems, 2002
2000
Proceedings of the Progress in Cryptology, 2000