Ashraf Salem

Orcid: 0000-0002-7971-1707

According to our database1, Ashraf Salem authored at least 47 papers between 2000 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Increasing the Modeling Accuracy of an Analog PLL Device Executed With an Event-Driven Simulator.
IEEE Access, 2023

2022
A Multicycle Pipelined GCM-Based AUTOSAR Communication ASIP.
IEEE Access, 2022

Towards a Digital Twin Architecture with Formal Analysis Capabilities for Learning-Enabled Autonomous Systems.
Proceedings of the Modelling and Simulation for Autonomous Systems, 2022

2021
Multimodal Video Sentiment Analysis Using Deep Learning Approaches, a Survey.
Inf. Fusion, 2021

Using Path Planning Algorithms and Digital Twin Simulators to Collect Synthetic Training Dataset for Drone Autonomous Navigation.
Proceedings of the 28th IEEE International Conference on Electronics, 2021

2020
Anomaly Detection System for Altered Signal Values within the Intra-Vehicle Network.
Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020

2019
Fast Transaction-Level Model for Direct Memory Access Controller.
J. Circuits Syst. Comput., 2019

Virtual Verification and Validation of Automotive System.
J. Circuits Syst. Comput., 2019

PLL Real Number Modeling in SystemVerilog.
Proceedings of the 16th International Conference on Synthesis, 2019

2018
Fuzzy-based configuration of automated data acquisition systems for earthmoving operations.
J. Inf. Technol. Constr., 2018

Cross-product functional coverage analysis using machine learning clustering techniques.
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

2016
Formal Based Methodology for Inferring Memory Mapped Registers.
Proceedings of the 17th International Workshop on Microprocessor and SOC Test and Verification, 2016

SoC connectivity specification extraction using incomplete RTL design: An approach for Formal connectivity Verification.
Proceedings of the 11th International Design & Test Symposium, 2016

AUTOSAR-based communication coprocessor for automotive ECUs.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Toward the interfacing of systemC-AMS models with hardware-emulated platforms.
Proceedings of the 10th International Design & Test Symposium, 2015

Automatic test pattern generation for virtual hardware model using constrained symbolic execution.
Proceedings of the 10th International Design & Test Symposium, 2015

SoC verification platforms using HW emulation and co-modeling Testbench technologies.
Proceedings of the 10th International Design & Test Symposium, 2015

Solving constraints in FPGA detailed routing using SMT.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2014
Don't cares based dynamic test vector compaction in SAT-ATPG.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Efficient embedded SoC hardware/software codesign using virtual platform.
Proceedings of the 9th International Design and Test Symposium, 2014

Formal verification of AUTOSAR FlexRay state manager.
Proceedings of the 9th International Design and Test Symposium, 2014

2013
Ultra-Fast DMAC TLM Model for High Speed Virtual Platform Simulation.
Proceedings of the 14th International Workshop on Microprocessor Test and Verification, 2013

A novel approach for functional verification of memory protocol standard.
Proceedings of the 8th International Design and Test Symposium, 2013

Tutorial 1: Foundations and Practical Design of CMOS Image Sensors.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

A novel approach for assertion based verification of DDR memory protocols.
Proceedings of the 2013 Forum on specification and Design Languages, 2013

2011
TLM Based Approach for Architecture Exploration of Multicore Systems-on-Chip.
Proceedings of the 12th International Workshop on Microprocessor Test and Verification, 2011

A reconfigurable, pipelined, conflict directed jumping search SAT solver.
Proceedings of the Design, Automation and Test in Europe, 2011

A novel approach for system level synthesis of multi-core system architectures from TPG models.
Proceedings of the 9th IEEE/ACS International Conference on Computer Systems and Applications, 2011

2010
Efficient partitioning technique on multiple cores based on optimal scheduling and mapping algorithm.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A novel conflict directed jumping algorithm for hardware-based SAT solvers.
Proceedings of the 5th International Design and Test Workshop, 2010

2009
Optimal Scheme for Search State Space and Scheduling on Multiprocessor Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

A Reconfigurable Five-Stage Pipelined SAT Solver.
Proceedings of the 10th International Workshop on Microprocessor Test and Verification, 2009

2008
TLM-Based Verification of a Combined Switching Networks-on-Chip Router.
Proceedings of the Forum on specification and Design Languages, 2008

Hardware based algorithm for conflict diagnosis in SAT solver.
Proceedings of the 6th ACS/IEEE International Conference on Computer Systems and Applications, 2008

2007
A Platform Approach for Hardware/Software Co-Design with Support for RTOS-Based Systems.
J. Circuits Syst. Comput., 2007

Interactive presentation: A shift register based clause evaluator for reconfigurable SAT solver.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
FPGA-Based SAT Solver.
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

2005
An FPGA Based Accelerator for SAT Based Combinational Equivalence Checking.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

FPGA Based Accelerator for 3-SAT Conflict Analysis in SAT Solvers.
Proceedings of the Correct Hardware Design and Verification Methods, 2005

2004
Formal Verification of Digital Circuits.
Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004

Towards Automating Hardware/Software Co-Design.
Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004

2003
Formal Semantics of Synchronous SystemC.
Proceedings of the 2003 Design, 2003

2002
Semi-formal verification of VHDL-AMS descriptions.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
On the use of don't cares during symbolic reachability analysis.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

UML-L: An UML Based Design Description Language.
Proceedings of the 2001 ACS / IEEE International Conference on Computer Systems and Applications (AICCSA 2001), 2001

2000
M-CHECK: a multiple engine combinational equivalence checker.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

An oscillating algorithm for variable ordering in binary decision diagram.
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000


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