Masaharu Imai
According to our database1,
Masaharu Imai
authored at least 84 papers
between 1979 and 2023.
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Bibliography
2023
EMoDi: Entity-Enhanced Momentum-Difference Contrastive Learning for Semantic-Aware Verification of Scientific Information.
Proceedings of the IEEE International Conference on Knowledge Graph, 2023
2018
Decomposed Vector Histograms of Oriented Gradients for Efficient Hardware Implementation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018
2017
A Low-Energy Application Specific Instruction-Set Processor towards a Low-Computational Lossless Compression Method for Stimuli Position Data of Artificial Vision Systems.
J. Inf. Process., 2017
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
Flexible sensor sheet for real-time pressure monitoring in artificial knee joint during total knee arthroplasty.
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017
Emerging technologies for biomedical applications: Artificial vision systems and brain machine interface.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
A programmable controller for spatio-temporal pattern stimulation of cortical visual prosthesis.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016
2015
An Efficient Performance Estimation Method for Configurable Multi-layer Bus-based SoC.
IPSJ Trans. Syst. LSI Des. Methodol., 2015
Preliminary study of a new home healthcare monitoring to prevent the recurrence of stroke.
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015
Cortical neural excitations in rats in vivo with using a prototype of a wireless multi-channel microstimulation system.
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015
A low-energy ASIP with flexible exponential Golomb codec for lossless data compression toward artificial vision systems.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015
2014
IEICE Trans. Commun., 2014
An efficient data compression method for artificial vision systems and its low energy implementation using ASIP technology.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014
2013
J. Ambient Intell. Humaniz. Comput., 2013
Proceedings of the International Conference on Information Networking 2013, 2013
An efficient lossless data compression method based on exponential-Golomb coding for biomedical information and its implementation using ASIP technology.
Proceedings of the 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), Rotterdam, The Netherlands, October 31, 2013
Error analysis of an estimation method using RTT for available bandwidth of a bottleneck link.
Proceedings of the 15th Asia-Pacific Network Operations and Management Symposium, 2013
2012
A Small-Area and Low-Power SoC for Less-Invasive Pressure Sensing Capsules in Ambulatory Urodynamic Monitoring.
IEICE Trans. Electron., 2012
Proceedings of the IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, 2012
Task Allocation and Scheduling for Voltage-Frequency Islands Applied NoC-based MPSoC Considering Network Congestion.
Proceedings of the IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, 2012
2011
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
Proceedings of the International SoC Design Conference, 2011
Biological information sensing technologies for medical, health care, and wellness applications.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
Proceedings of the 2011 International Conference on P2P, 2011
2010
Software Development Tool Generation Method Suitable for Instruction Set Extension of Embedded Processors.
IPSJ Trans. Syst. LSI Des. Methodol., 2010
IPSJ Trans. Syst. LSI Des. Methodol., 2010
Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP).
IPSJ Trans. Syst. LSI Des. Methodol., 2010
Efficient partitioning technique on multiple cores based on optimal scheduling and mapping algorithm.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Two-stage configurable decoder model for multiple forward error correction standards.
Proceedings of the 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Heuristic Instruction Scheduling Algorithm Using Available Distance for Partial Forwarding Processor.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008
2007
Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors.
ACM Trans. Design Autom. Electr. Syst., 2007
Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
Proceedings of the IEEE International Conference on Acoustics, 2007
A low power VLIW processor generation method by means of extracting non-redundant activation conditions.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007
A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
Task Partitioning Oriented Architecture Exploration Method for Dynamic Reconfigurable Architectures.
Proceedings of the IFIP VLSI-SoC 2006, 2006
Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model.
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006
2005
Operation Shuffling for Low Energy L0 Cluster Generation on Heterogeneous VLIW Processors.
Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005
Proceedings of the 2005 Design, 2005
Proceedings of the Correct Hardware Design and Verification Methods, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
S-sequence: a new floorplan representation method preserving room abutment relationships.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 24th International Conference on Distributed Computing Systems Workshops (ICDCS 2004 Workshops), 2004
Proceedings of the 2004 Design, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
Proceedings of the Software and Compilers for Embedded Systems, 7th International Workshop, 2003
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003
2002
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
Proceedings of the 13th IEEE International Workshop on Rapid System Prototyping (RSP 2002), 2002
Design space exploration for DSP applications using the ASIP development system PEAS-III.
Proceedings of the IEEE International Conference on Acoustics, 2002
2001
Proceedings of the 27th EUROMICRO Conference 2001: A Net Odyssey, 2001
Proceedings of ASP-DAC 2001, 2001
2000
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000
Proceedings of ASP-DAC 2000, 2000
1999
A programmable processor with multiple functional units and banked registers for general purpose numerical processing.
Proceedings of the 1999 IEEE International Conference on Acoustics, 1999
Proceedings of the 25th EUROMICRO '99 Conference, 1999
1998
A Performance Maximization Algorithm to Design ASIPs under the Constraint of Chip Area Including RAM and ROM Sizes.
Proceedings of the ASP-DAC '98, 1998
1997
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
1996
Syst. Comput. Jpn., 1996
ASPDAC 1995: HDL synthesizability and interoperability.
IEEE Des. Test Comput., 1996
A new HW/SW partitioning algorithm for synthesizing the highest performance pipelined ASIPs with multiple identical FUs.
Proceedings of the conference on European design automation, 1996
A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts.
Proceedings of the 33st Conference on Design Automation, 1996
1995
Proceedings of the Proceedings EURO-DAC'95, 1995
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995
A hardware/software codesign method for pipelined instruction set processor using adaptive database.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995
1993
An ASIP instruction set optimization algorithm with functional module sharing constraint.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993
Proceedings of the European Design Automation Conference 1993, 1993
1992
An integer programming approach to instruction implementation method selection problem.
Proceedings of the conference on European design automation, 1992
1991
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991
1988
Computational complexity of the file allocation problem in distributed database systems.
Syst. Comput. Jpn., 1988
Syst. Comput. Jpn., 1988
1987
1986
Implementation of Parallel Prolog on Tree Machines.
Proceedings of the Fall Joint Computer Conference, November 2-6, 1986, Dallas, Texas, USA, 1986
1984
The Architecture and Efficiency of DON: A Combinatorial Problem Oriented Multicomputer System.
Proceedings of the 4th International Conference on Distributed Computing Systems, 1984
1979
A Parallel Searching Scheme for Multiprocessor Systems and Its Application to Combinatorial Problems.
Proceedings of the Sixth International Joint Conference on Artificial Intelligence, 1979