Asmit De

Orcid: 0000-0002-8175-1337

According to our database1, Asmit De authored at least 18 papers between 2015 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
HeapSafe: Securing Unprotected Heaps in RISC-V.
Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022

2021
SecNVM: Power Side-Channel Elimination Using On-Chip Capacitors for Highly Secure Emerging NVM.
IEEE Trans. Very Large Scale Integr. Syst., 2021

2020
Cache-Out: Leaking Cache Memory Using Hardware Trojan.
IEEE Trans. Very Large Scale Integr. Syst., 2020

HarTBleed: Using Hardware Trojans for Data Leakage Exploits.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Threshold-Defined Logic and Interconnect for Protection Against Reverse Engineering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Hardware Assisted Buffer Protection Mechanisms for Embedded RISC-V.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

TrappeD: DRAM Trojan Designs for Information Leakage and Fault Injection Attacks.
CoRR, 2020

Recent Advances in Emerging Technology-based Security Primitives, Attacks and Mitigation.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Power Side Channel Attack Analysis and Detection.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019
RF-Trojan: Leaking Kernel Data Using Register File Trojan.
CoRR, 2019

FIXER: Flow Integrity Extensions for Embedded RISC-V.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
CTCG: Charge-trap based camouflaged gates for reverse engineering prevention.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

2017
Replacing eFlash with STTRAM in IoTs: Security Challenges and Solutions.
J. Hardw. Syst. Secur., 2017

Threshold voltage defined multi-input complex gates.
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

2016
Cache Bypassing and Checkpointing to Circumvent Data Security Attacks on STTRAM.
CoRR, 2016

Attack resilient architecture to replace embedded Flash with STTRAM in homogeneous IoTs.
CoRR, 2016

Security and privacy threats to on-chip non-volatile memories and countermeasures.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015
Towards the hierarchical design of multilayer QCA logic circuit.
J. Comput. Sci., 2015


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