Swaroop Ghosh

According to our database1, Swaroop Ghosh authored at least 148 papers between 2003 and 2020.

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Bibliography

2020
Cache-Out: Leaking Cache Memory Using Hardware Trojan.
IEEE Trans. Very Large Scale Integr. Syst., 2020

HarTBleed: Using Hardware Trojans for Data Leakage Exploits.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Design, Analysis and Application of Embedded Resistive RAM Based Strong Arbiter PUF.
IEEE Trans. Dependable Secur. Comput., 2020

Threshold-Defined Logic and Interconnect for Protection Against Reverse Engineering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Addressing Resiliency of In-Memory Floating Point Computation.
CoRR, 2020

SCARE: Side Channel Attack on In-Memory Computing for Reverse Engineering.
CoRR, 2020

TrappeD: DRAM Trojan Designs for Information Leakage and Fault Injection Attacks.
CoRR, 2020

Domain Wall Memory-Based Design of Deep Neural Network Convolutional Layers.
IEEE Access, 2020

Recent Advances in Emerging Technology-based Security Primitives, Attacks and Mitigation.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Circuit Compilation Methodologies for Quantum Approximate Optimization Algorithm.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

Hierarchical Improvement of Quantum Approximate Optimization Algorithm for Object Detection: (Invited Paper).
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Multi-Bit Read and Write Methodologies for Diode-MTJ Crossbar Array.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

A Morphable Physically Unclonable Function and True Random Number Generator using a Commercial Magnetic Memory.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Improving Reliability of Quantum True Random Number Generator using Machine Learning.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Resiliency analysis and improvement of variational quantum factoring in superconducting qubit.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

Analysis of crosstalk in NISQ devices and security implications in multi-programming regime.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

FAuto: An Efficient GMM-HMM FPGA Implementation for Behavior Estimation in Autonomous Systems.
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020

Quantum-Soft QUBO Suppression for Accurate Object Detection.
Proceedings of the Computer Vision - ECCV 2020, 2020

Accelerating Quantum Approximate Optimization Algorithm using Machine Learning.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

An Efficient Circuit Compilation Flow for Quantum Approximate Optimization Algorithm.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Design-Space Exploration of Quantum Approximate Optimization Algorithm under Noise.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019
Guest Editorial Special Section on Security Challenges and Solutions With Emerging Computing Technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Cache Bypassing and Checkpointing to Circumvent Data Security Attacks on STTRAM.
IEEE Trans. Emerg. Top. Comput., 2019

ROBIN: Monolithic-3D SRAM for Enhanced Robustness with In-Memory Computation Support.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Family of Compact Non-Volatile Flip-Flops With Ferroelectric FET.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

TCAD EIC Message: February 2019.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Sensitivity-Based Error Resilient Techniques With Heterogeneous Multiply-Accumulate Unit for Voltage Scalable Deep Neural Network Accelerators.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

A Perspective on Test Methodologies for Supervised Machine Learning Accelerators.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

Analysis of Quantum Approximate Optimization Algorithm under Realistic Noise in Superconducting Qubits.
CoRR, 2019

RF-Trojan: Leaking Kernel Data Using Register File Trojan.
CoRR, 2019

Study of Decoherence in Quantum Computers: A Circuit-Design Perspective.
CoRR, 2019

Logic Obfuscation using Metasurface Holography.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

iMACE: In-Memory Acceleration of Classic McEliece Encoder.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

SHINE: A Novel SHA-3 Implementation Using ReRAM-based In-Memory Computing.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Addressing Temporal Variations in Qubit Quality Metrics for Parameterized Quantum Circuits.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Meeting the Conflicting Goals of Low-Power and Resiliency Using Emerging Memories : (Invited Paper).
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

FPCAS: In-Memory Floating Point Computations for Autonomous Systems.
Proceedings of the International Joint Conference on Neural Networks, 2019

MUQUT: Multi-Constraint Quantum Circuit Mapping on NISQ Computers: Invited Paper.
Proceedings of the International Conference on Computer-Aided Design, 2019

ENTT: A Family of Emerging NVM-based Trojan Triggers.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019

TOIC: Timing Obfuscated Integrated Circuits.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

True Random Number Generator using Superconducting Qubits.
Proceedings of the Device Research Conference, 2019

Hardware Trojans in Emerging Non-Volatile Memories.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

FIXER: Flow Integrity Extensions for Embedded RISC-V.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Sensitivity based Error Resilient Techniques for Energy Efficient Deep Neural Network Accelerators.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

QURE: Qubit Re-allocation in Noisy Intermediate-Scale Quantum Computers.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Novel Magnetic Burn-In for Retention and Magnetic Tolerance Testing of STTRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2018

CSRO-Based Reconfigurable True Random Number Generator Using RRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2018

VFAB: A Novel 2-Stage STTRAM Sensing Using Voltage Feedback and Boosting.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Magnetic Tunnel Junction Reliability Assessment Under Process Variations and Activity Factors and Mitigation Techniques.
J. Low Power Electron., 2018

Impact of Process Variation on Self-Reference Sensing Scheme and Adaptive Current Modulation for Robust STTRAM Sensing.
ACM J. Emerg. Technol. Comput. Syst., 2018

Test challenges and solutions for emerging non-volatile memories.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Test of Supply Noise for Emerging Non-Volatile Memory.
Proceedings of the IEEE International Test Conference, 2018

A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

Information Leakage Attacks on Emerging Non-Volatile Memory and Countermeasures.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

Threshold Defined Camouflaged Gates in 65nm Technology for Reverse Engineering Protection.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

Fault injection attacks on emerging non-volatile memory and countermeasures.
Proceedings of the 7th International Workshop on Hardware and Architectural Support for Security and Privacy, 2018

Dynamic Computing in Memory (DCIM) in Resistive Crossbar Arrays.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

Analysis of Row Hammer Attack on STTRAM.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

How Multi-Threshold Designs Can Protect Analog IPs.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

CTCG: Charge-trap based camouflaged gates for reverse engineering prevention.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

Novel application of spintronics in computing, sensing, storage and cybersecurity.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Replacing eFlash with STTRAM in IoTs: Security Challenges and Solutions.
J. Hardw. Syst. Secur., 2017

Design and Analysis of STTRAM-Based Ternary Content Addressable Memory Cell.
ACM J. Emerg. Technol. Comput. Syst., 2017

A Novel Interconnect Camouflaging Technique using Transistor Threshold Voltage.
CoRR, 2017

Methodologies to exploit ATPG tools for de-camouflaging.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Investigation of magnetic field attacks on commercial Magneto-Resistive Random Access Memory.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Side-Channel Attack on STTRAM Based Cache for Cryptographic Application.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Threshold voltage defined multi-input complex gates.
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

Novel magnetic burn-in for retention testing of STTRAM.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Droop mitigating last level cache architecture for STTRAM.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Session 13 - Security circuits and systems.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
Adaptive Write and Shift Current Modulation for Process Variation Tolerance in Domain Wall Caches.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Exploiting Serial Access and Asymmetric Read/Write of Domain Wall Memory for Area and Energy-Efficient Digital Signal Processor Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Spintronics and Security: Prospects, Vulnerabilities, Attack Models, and Preventions.
Proc. IEEE, 2016

Robust Self-Collapsing Level-Shifter for Wide Voltage Operation.
J. Low Power Electron., 2016

Spintronic PUFs for Security, Trust, and Authentication.
ACM J. Emerg. Technol. Comput. Syst., 2016

Guest Editorial Emerging Memories - Technology, Architecture and Applications (Second Issue).
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Guest Editorial Emerging Memories - Technology, Architecture and Applications (First Issue).
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Overview of Circuits, Systems, and Applications of Spintronics.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Retention Testing Methodology for STTRAM.
IEEE Des. Test, 2016

Side Channel Attacks on STTRAM and Low-Overhead Countermeasures.
CoRR, 2016

Cache Bypassing and Checkpointing to Circumvent Data Security Attacks on STTRAM.
CoRR, 2016

Multi-Bit Read and Write Methodologies for Diode-STTRAM Crossbar Array.
CoRR, 2016

Attack resilient architecture to replace embedded Flash with STTRAM in homogeneous IoTs.
CoRR, 2016

A strong arbiter PUF using resistive RAM.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Performance Impact of Magnetic and Thermal Attack on STTRAM and Low-Overhead Mitigation Techniques.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Domain Wall Memory based Convolutional Neural Networks for Bit-width Extendability and Energy-Efficiency.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

A strong arbiter PUF using resistive RAM within 1T-1R memory architecture.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Security and privacy threats to on-chip non-volatile memories and countermeasures.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

A novel threshold voltage defined switch for circuit camouflaging.
Proceedings of the 21th IEEE European Test Symposium, 2016

Side channel attacks on STTRAM and low-overhead countermeasures.
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

Data privacy in non-volatile cache: Challenges, attack models and solutions.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
MTJ-Based State Retentive Flip-Flop With Enhanced-Scan Capability to Sustain Sudden Power Failure.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Emerging Trends in Design and Applications of Memory-Based Computing and Content-Addressable Memories.
Proc. IEEE, 2015

A 1 Gb 2 GHz 128 GB/s Bandwidth Embedded DRAM in 22 nm Tri-Gate CMOS Technology.
IEEE J. Solid State Circuits, 2015

Domain Wall Magnets for Embedded Memory and Hardware Security.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

How Secure Are Printed Circuit Boards Against Trojan Attacks?
IEEE Des. Test, 2015

Schmitt-Trigger-based Recycling Sensor and Robust and High-Quality PUFs for Counterfeit IC Detection.
CoRR, 2015

Threshold Voltage-Defined Switches for Programmable Gates.
CoRR, 2015

Spintronics for associative computation and hardware security.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Novel self-calibrating recycling sensor using Schmitt-Trigger and voltage boosting for fine-grained detection.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Design and analysis of novel SRAM PUFs with embedded latch for robustness.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

A novel slope detection technique for robust STTRAM sensing.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Design and analysis of 6-T 2-MTJ ternary Content Addressable Memory.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

A family of Schmitt-Trigger-based arbiter-PUFs and selective challenge-pruning for robustness and quality.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

Impact of process-variations in STTRAM and adaptive boosting for robustness.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Self-correcting STTRAM under magnetic field attacks.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Domain wall memory based digital signal processors for area and energy-efficiency.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Modeling of Retention Time for High-Speed Embedded Dynamic Random Access Memories.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Energy Barrier Model of SRAM for Improved Energy and Error Rates.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Tutorial T6B: Embedded Memory Design for Future Technologies: Challenges and Solutions.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Synergistic circuit and system design for energy-efficient and robust domain wall caches.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

DWM-PUF: A low-overhead, memory-based security primitive.
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

Design and analysis of robust and wide operating low-power level-shifter for embedded dynamic random access memory.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Simultaneous Sizing, Reference Voltage and Clamp Voltage Biasing for Robustness, Self-Calibration and Testability of STTRAM Arrays.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Modeling and Analysis of Domain Wall Dynamics for Robust and Low-Power Embedded Memory.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Design methodologies for high density domain wall memory.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

Path to a TeraByte of on-chip memory for petabit per second bandwidth with < 5watts of power.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Energy centric model of SRAM write operation for improved energy and error rates.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2011
Novel Low Overhead Post-Silicon Self-Correction Technique for Parallel Prefix Adders Using Selective Redundancy and Adaptive Clocking.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Integrated Design & Test: Conquering the Conflicting Requirements of Low-Power, Variation-Tolerance and Test Cost.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Effect of Variations and Variation Tolerance in Logic Circuits.
Proceedings of the Low-Power Variation-Tolerant Design in Nanometer Silicon, 2011

2010
Trifecta: A Nonspeculative Scheme to Exploit Common, Data-Dependent Subcritical Paths.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Voltage Scalable High-Speed Robust Hybrid Arithmetic Units Using Adaptive Clocking.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Parameter Variation Tolerance and Error Resiliency: New Design Paradigm for the Nanoscale Era.
Proc. IEEE, 2010

2009
Coping with Variations through System-Level Design.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

2008
An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs.
ACM J. Emerg. Technol. Comput. Syst., 2008

O<sup>2</sup>C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking.
Proceedings of the Design, Automation and Test in Europe, 2008

Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Low-Power and testable circuit synthesis using Shannon decomposition.
ACM Trans. Design Autom. Electr. Syst., 2007

CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

A generic and reconfigurable test paradigm using Low-cost integrated Poly-Si TFTs.
Proceedings of the 2007 IEEE International Test Conference, 2007

Tolerance to Small Delay Defects by Adaptive Clock Stretching.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Process-Tolerant Low-Power Adaptive Pipeline under Scaled-Vdd.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Low-Power and Process Variation Tolerant Memories in sub-90nm Technologies.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM.
Proceedings of the 43rd Design Automation Conference, 2006

2005
A built-in self-testing method for embedded multiport memory arrays.
IEEE Trans. Instrum. Meas., 2005

A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

A novel delay fault testing methodology using on-chip low-overhead delay measurement hardware at strategic probe points.
Proceedings of the 10th European Test Symposium, 2005

Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004
Scan Chain Fault Identification Using Weight-Based Codes for SoC Circuits.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003
Embedded core test generation using broadcast test architecture and netlist scrambling.
IEEE Trans. Reliab., 2003


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