Anirudh Iyengar

According to our database1, Anirudh Iyengar authored at least 19 papers between 2014 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
A Reference-less Slope Detection Technique in 65nm for Robust Sensing of 1T1R Arrays.
CoRR, 2023

2020
Threshold-Defined Logic and Interconnect for Protection Against Reverse Engineering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2018
Novel Magnetic Burn-In for Retention and Magnetic Tolerance Testing of STTRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Magnetic Tunnel Junction Reliability Assessment Under Process Variations and Activity Factors and Mitigation Techniques.
J. Low Power Electron., 2018

Threshold Defined Camouflaged Gates in 65nm Technology for Reverse Engineering Protection.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

CTCG: Charge-trap based camouflaged gates for reverse engineering prevention.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

2017
Novel magnetic burn-in for retention testing of STTRAM.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Spintronic PUFs for Security, Trust, and Authentication.
ACM J. Emerg. Technol. Comput. Syst., 2016

Overview of Circuits, Systems, and Applications of Spintronics.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Retention Testing Methodology for STTRAM.
IEEE Des. Test, 2016

A novel threshold voltage defined switch for circuit camouflaging.
Proceedings of the 21th IEEE European Test Symposium, 2016

Side channel attacks on STTRAM and low-overhead countermeasures.
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

Data privacy in non-volatile cache: Challenges, attack models and solutions.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
MTJ-Based State Retentive Flip-Flop With Enhanced-Scan Capability to Sustain Sudden Power Failure.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Domain Wall Magnets for Embedded Memory and Hardware Security.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Threshold Voltage-Defined Switches for Programmable Gates.
CoRR, 2015

2014
Synergistic circuit and system design for energy-efficient and robust domain wall caches.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

DWM-PUF: A low-overhead, memory-based security primitive.
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

Modeling and Analysis of Domain Wall Dynamics for Robust and Low-Power Embedded Memory.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014


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