Balkaran S. Gill

According to our database1, Balkaran S. Gill authored at least 7 papers between 2004 and 2007.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2007
Interactive presentation: A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Combinational Logic Soft Error Correction.
Proceedings of the 2006 IEEE International Test Conference, 2006

Soft delay error analysis in logic circuits.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Node sensitivity analysis for soft errors in CMOS logic.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Radiation Induced Single-Word Multiple-Bit Upsets Correction in SRAM.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories.
Proceedings of the 2005 Design, 2005

2004
Soft Delay Error Effects in CMOS Combinational Circuits.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004


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