Bill Underwood

According to our database1, Bill Underwood authored at least 11 papers between 1984 and 2003.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2003
Speed Binning with Path Delay Test in 150-nm Technology.
IEEE Des. Test Comput., 2003

1994
Fastpath: A Path-Delay Test Generator for Standard Scan Designs.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

Path-Delay Fault Simulation for a Standard Scan Design Methodology.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

1991
Delay Testing Quality in Timing-Optimized Designs.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

The Interdependence Between Delay-Optimization of Synthesized Networks and Testing.
Proceedings of the 28th Design Automation Conference, 1991

1989
The Parallel-Test-Detect Fault Simulation Algorithm.
Proceedings of the Proceedings International Test Conference 1989, 1989

1988
D^3FS: A Demand Driven Deductive Fault Simulator.
Proceedings of the Proceedings International Test Conference 1988, 1988

An Analysis of Parallel Logic Simulation on Several Architectures.
Proceedings of the International Conference on Parallel Processing, 1988

1986
Calculation of Greatest Lower Bounds Obtainable by the Cutting Algorithm.
Proceedings of the Proceedings International Test Conference 1986, 1986

1985
Built-In Self Test Input Generator for Programmable Logic Arrays.
Proceedings of the Proceedings International Test Conference 1985, 1985

1984
Correlating Testability with Fault Detection.
Proceedings of the Proceedings International Test Conference 1984, 1984


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