Chang-Hyeon Lee

According to our database, Chang-Hyeon Lee authored at least 5 papers between 1999 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

A 2.7 GHz to 7 GHz Fractional-N LC-PLL Utilizing Multi-Metal Layer SoC Technology in 28 nm CMOS.

Chang-Hyeon Lee, Lindel Kabalican, Yan Ge, Hendra Kwantono, Greg Unruh, Mark Chambers, Ichiro Fujimori

IEEE J. Solid State Circuits, 2015

2014

A 2.7GHz to 7GHz fractional-N LCPLL utilizing multimetal layer SoC technology in 28nm CMOS.

Chang-Hyeon Lee, Lindel Kabalican, Yan Ge, Hendra Kwantono, Greg Unruh, Mark Chambers, Ichiro Fujimori

Proceedings of the Symposium on VLSI Circuits, 2014

2012

A 40 nm CMOS analog front end with enhanced audio for HSPA/EDGE multimedia applications.

Xicheng Jiang, Min-Gyu Kim, Felix Cheung, Fang Lin, Hui Zheng, Jianlong Chen, Alex Jianzhong Chen, Darwin Cheung, Khaled Abdelfattah, Seong-Ho Lee, Hanson Hung-Sen Huang, Kishore Kasichainula, Yonghua Cong, Jiangfeng Wu, Chang-Hyeon Lee, George Chih, Yun Tu, Todd Brooks, Edison Jiang, Hongwei Kong, Chaoyang Zhao, Mustafa Keskin

Proceedings of the 38th European Solid-State Circuit conference, 2012

2001

A supply-noise-insensitive CMOS PLL with a voltage regulator using DC-DC capacitive converter.

Chang-Hyeon Lee, Kelly McClellan, John Choma Jr.

IEEE J. Solid State Circuits, 2001

1999

Supply noise insensitive bandgap regulator using capacitive charge pump DC-DC converter.

Chang-Hyeon Lee, K. McCellan, John Choma Jr.

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999