Hung Sen Huang

According to our database, Hung Sen Huang authored at least 6 papers between 2012 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2016

A 2.7 mW/Channel 48-1000 MHz Direct Sampling Full-Band Cable Receiver.

Jiangfeng Wu, Giuseppe Cusmai, Acer Wei-Te Chou, Tao Wang, Bo Shen, Vijayaramalingam Periasamy, Ming-Hung Hsieh, Chun-Ying Chen, Lin He, Loke Kun Tan, Aravind Padyana, Vincent Cheng-Hsun Yang, Gregory Unruh, Jackie Koon Lun Wong, Bryan Juo-Jung Hung, Massimo Brandolini, Maco Sha-Ting Lin, Xi Chen, Yen Ding, Yen-Jen Ko, Young J. Shin, Ada Hing T. Hung, Binning Chen, Cynthia Dang, Deepak Lakshminarasimhan, Iris Hong Liu, Jerry Lin, Kowen Lai, Larry Wassermann, Ayaskant Shrivastava, Chi-Ming Hsiao, Chun-Sheng Huang, Jianlong Chen, Lakshminarasimhan Krishnan, Ning-Yi Wang, Pin-En Su, Tianwei Li, Wei-Ta Shih, Yau-Cheng Yang, Peter Cangiane, Randall Perlow, William Ngai, Hanson Hung-Sen Huang, James Y. C. Chang, Xicheng Jiang, Ardie G. Venes, Ramon Ray Gomez

IEEE J. Solid State Circuits, 2016

27.6 A 4GS/s 13b pipelined ADC with capacitor and amplifier sharing in 16nm CMOS.

Jiangfeng Wu, Acer Wei-Te Chou, Tianwei Li, Rong Wu, Tao Wang, Giuseppe Cusmai, Sha-Ting Lin, Cheng-Hsun Yang, Greg Unruh, Sunny Raj Dommaraju, Mo M. Zhang, Po Tang Yang, Wei-Ting Lin, Xi Chen, Dongsoo Koh, Qingqi Dou, Hemasundar Mohan Geddada, Juo-Jung Hung, Massimo Brandolini, Young Shin, Hung Sen Huang, Chun-Ying Chen, Ardie G. Venes

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

A 5 GS/s 150 mW 10 b SHA-Less Pipelined/SAR Hybrid ADC for Direct-Sampling Systems in 28 nm CMOS.

Massimo Brandolini, Young Shin, Karthik Raviprakash, Tao Wang, Rong Wu, Hemasundar Mohan Geddada, Yen-Jen Ko, Yen Ding, Chun-Sheng Huang, Wei-Ta Shih, Ming-Hung Hsieh, Wei-Te Chou, Tianwei Li, Ayaskant Shrivastava, Yi-Chun Chen, Bryan Juo-Jung Hung, Giuseppe Cusmai, Jiangfeng Wu, Mo M. Zhang, Yuan Yao, Greg Unruh, Ardie G. Venes, Hung Sen Huang, Chun-Ying Chen

IEEE J. Solid State Circuits, 2015

A 2.7mW/Channel 48-to-1000MHz Direct Sampling Full-Band Cable Receiver.

Jiangfeng Wu, Giuseppe Cusmai, Acer Wei-Te Chou, Tao Wang, Bo Shen, Vijayaramalingam Periasamy, Ming-Hung Hsieh, Chun-Ying Chen, Lin He, Loke Tan, Aravind Padyana, Cheng-Hsun Yang, Gregory Unruh, Jackie Koon Lun Wong, Juo-Jung Hung, Massimo Brandolini, Sha-Ting Lin, Xi Chen, Yen Ding, Yen-Jen Ko, Young Shin, Ada Hing T. Hung, Binning Chen, Cynthia Dang, Deepak Lakshminarasimhan, Iris Hong Liu, Jerry Lin, Kowen Lai, Larry Wassermann, Ayaskant Shrivastava, Chi-Ming Hsiao, Chun-Sheng Huang, Jianlong Chen, Lakshminarasimhan Krishnan, Ning-Yi Wang, Pin-En Su, Tianwei Li, Wei-Ta Shih, Yau-Cheng Yang, Peter Cangiane, Randall Perlow, William Ngai, Hung Sen Huang, James Y. C. Chang, Xicheng Jiang, Ardie G. Venes, Ramon Gomez

Proceedings of the Symposium on VLSI Circuits, 2015

26.6 A 5GS/S 150mW 10b SHA-less pipelined/SAR hybrid ADC in 28nm CMOS.

Massimo Brandolini, Young Shin, Karthik Raviprakash, Tao Wang, Rong Wu, Hemasundar Mohan Geddada, Yen-Jen Ko, Yen Ding, Chun-Sheng Huang, Wei-Ta Shih, Ming-Hung Hsieh, Wei-Te Chou, Tianwei Li, Ayaskant Shrivastava, Yi-Chun Chen, Juo-Jung Hung, Giuseppe Cusmai, Jiangfeng Wu, Mo M. Zhang, Greg Unruh, Ardie G. Venes, Hung Sen Huang, Chun-Ying Chen

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2012

A 40 nm CMOS analog front end with enhanced audio for HSPA/EDGE multimedia applications.

Xicheng Jiang, Min-Gyu Kim, Felix Cheung, Fang Lin, Hui Zheng, Jianlong Chen, Alex Jianzhong Chen, Darwin Cheung, Khaled Abdelfattah, Seong-Ho Lee, Hanson Hung-Sen Huang, Kishore Kasichainula, Yonghua Cong, Jiangfeng Wu, Chang-Hyeon Lee, George Chih, Yun Tu, Todd Brooks, Edison Jiang, Hongwei Kong, Chaoyang Zhao, Mustafa Keskin

Proceedings of the 38th European Solid-State Circuit conference, 2012