Chang-Ming Lai

According to our database1, Chang-Ming Lai authored at least 14 papers between 2006 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
10.4 A 4×4 Dual-Band Dual-Concurrent WiFi 802.11ax Transceiver with Integrated LNA, PA and T/R Switch Achieving +20dBm 1024-QAM MCS11 Pout and -43dB EVM Floor in 55nm CMOS.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2015
A 0.003 mm<sup>2</sup> 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching.
IEEE J. Solid State Circuits, 2015

2014
A UWB Impulse-Radio Timed-Array Radar With Time-Shifted Direct-Sampling Architecture in 0.18-µm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A mixed-signal phase-domain FSK demodulator for BLE single-path low-IF receiver.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

28.3 A frequency-defined vernier digital-to-time converter for impulse radar systems in 65nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A feedforward noise and distortion cancellation technique for CMOS broadband LNA-mixer.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
Time-domain analog-to-digital converters with domino delay lines.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

A scalable direct-sampling broadband radar receiver supporting simultaneous digital multibeam array in 65nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
A UWB IR timed-array radar using time-shifted direct-sampling architecture.
Proceedings of the Symposium on VLSI Circuits, 2012

2011
A low-power CMOS LNA using noise suppression and distortion cancellation techniques with inductive bandwidth extension.
Proceedings of the International SoC Design Conference, 2011

A 0.24 to 2.4 GHz phase-locked loop with low supply sensitivity in 0.18-µm CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A 90nm CMOS, 5.6ps, 0.23pJ/code time-to-digital converter with multipath oscillator and seamless cycle detection.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
A Quantization Error Minimization Method Using DDS-DAC for Wideband Fractional-N Frequency Synthesizer.
IEEE J. Solid State Circuits, 2010

2006
An OPLL-DDS based frequency synthesizer for DCS-1800 receiver.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006


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