Chang-Ming Lai

According to our database, Chang-Ming Lai authored at least 14 papers between 2006 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

10.4 A 4×4 Dual-Band Dual-Concurrent WiFi 802.11ax Transceiver with Integrated LNA, PA and T/R Switch Achieving +20dBm 1024-QAM MCS11 Pout and -43dB EVM Floor in 55nm CMOS.

Eric Lu, Wen-Kai Li, Zhiming Deng, Edris Rostami, Pi-An Wu, Keng-Meng Chang, Yu-Chen Chuang, Chang-Ming Lai, Yang-Chuan Chen, Tzu-Hsuin Peng, Tzung-Chuen Tsai, Hui-Hsien Liu, Chien-Chih Chiu, Bryan Huang, Yao-Chi Wang, Jing-Hong Conan Zhan, Osama Shana'a

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2015

A 0.003 mm² 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching.

Jen-Huan Tsai, Hui-Huan Wang, Yang-Chi Yen, Chang-Ming Lai, Yen-Ju Chen, Po-Chiun Huang, Ping-Hsuan Hsieh, Hsin Chen, Chao-Cheng Lee

IEEE J. Solid State Circuits, 2015

2014

A UWB Impulse-Radio Timed-Array Radar With Time-Shifted Direct-Sampling Architecture in 0.18-µm CMOS.

Chang-Ming Lai, Kai-Wen Tan, Yen-Ju Chen, Ta-Shun Chu

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A mixed-signal phase-domain FSK demodulator for BLE single-path low-IF receiver.

Cuei-Ling Hsieh, Chang-Ming Lai, Guan-Hong Ke, Jenny Yi-Chun Liu, Po-Chiun Huang

Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

28.3 A frequency-defined vernier digital-to-time converter for impulse radar systems in 65nm CMOS.

Yu-Hsien Kao, Chang-Ming Lai, Jen-Ming Wu, Po-Chiun Huang, Ping-Hsuan Hsieh, Ta-Shun Chu

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A feedforward noise and distortion cancellation technique for CMOS broadband LNA-mixer.

Chin-Fu Li, Shih-Chieh Chou, Chang-Ming Lai, Cuei-Ling Hsieh, Jenny Yi-Chun Liu, Po-Chiun Huang

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013

Time-domain analog-to-digital converters with domino delay lines.

Chang-Ming Lai, Yi-Chung Chen, Po-Chiun Huang

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

A scalable direct-sampling broadband radar receiver supporting simultaneous digital multibeam array in 65nm CMOS.

Chang-Ming Lai, Jen-Ming Wu, Po-Chiun Huang, Ta-Shun Chu

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012

A UWB IR timed-array radar using time-shifted direct-sampling architecture.

Chang-Ming Lai, Kai-Wen Tan, Liu-Yuan Yu, Yen-Ju Chen, Jun-Wei Huang, Shr-Chau Lai, Feng-Hsu Chung, Chia-Fung Yen, Jen-Ming Wu, Po-Chiun Huang, Keh-Jeng Chang, Shi-Yu Huang, Ta-Shun Chu

Proceedings of the Symposium on VLSI Circuits, 2012

2011

A low-power CMOS LNA using noise suppression and distortion cancellation techniques with inductive bandwidth extension.

Chin-Fu Li, Chang-Ming Lai, Ping-Chuan Chiang, Po-Chiun Huang

Proceedings of the International SoC Design Conference, 2011

A 0.24 to 2.4 GHz phase-locked loop with low supply sensitivity in 0.18-µm CMOS.

Chang-Ming Lai, Meng-Hung Shen, Yi-Da Wu, Kai-Hsiang Huang, Po-Chiun Huang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A 90nm CMOS, 5.6ps, 0.23pJ/code time-to-digital converter with multipath oscillator and seamless cycle detection.

Chang-Ming Lai, Meng-Hung Shen, Geng-Yi Pan, Po-Chiun Huang

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010

A Quantization Error Minimization Method Using DDS-DAC for Wideband Fractional-N Frequency Synthesizer.

Yi-Da Wu, Chang-Ming Lai, Chao-Cheng Lee, Po-Chiun Huang

IEEE J. Solid State Circuits, 2010

2006

An OPLL-DDS based frequency synthesizer for DCS-1800 receiver.

Yi-Da Wu, Chang-Ming Lai, Chih-Yuan Chou, Po-Chiun Huang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006