Chanho Lee

According to our database1, Chanho Lee
  • authored at least 12 papers between 2004 and 2016.
  • has a "Dijkstra number"2 of five.

Timeline

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Links

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Bibliography

2016
Design of Light-Weight High-Entropy Alloys.
Entropy, 2016

Design of eMMC controller with multiple channels.
Proceedings of the International SoC Design Conference, 2016

Digital clock data recovery circuit fot S/PDIF.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
An efficient memory control method for video and image processing in digital TV.
Displays, 2015

2014
Arbitration and shuffling algorithm for processing multiple commands in SDRAM controller.
Proceedings of the IEEE International Conference on Consumer Electronics, 2014

2009
A Phase-Based Approach for On-Chip Bus Architecture Optimization.
Comput. J., 2009

2007
A High-Speed Link Layer Architecture for Low Latency and Memory Cost Reduction.
Comput. J., 2007

2006
A High Performance SoC On-chip-bus with Multiple Channels and Routing Processes.
Proceedings of the IFIP VLSI-SoC 2006, 2006

2005
Efficient frequency-domain simulation technique for short-channel MOSFET.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

2004
A new multi-channel on-chip-bus architecture for system-on-chips.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Design of a programmable cryptoprocessor for multiple cryptosystems.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

High performance Viterbi decoder using modified register exchange methods.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004


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