Chanho Lee

Orcid: 0000-0002-4243-4988

According to our database1, Chanho Lee authored at least 21 papers between 2004 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
A 4.13-GHz UHS Pseudo Two-Port SRAM With BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4-nm FinFET Technology.
IEEE J. Solid State Circuits, April, 2024

FRED: Towards a Full Rotation-Equivariance in Aerial Image Object Detection.
Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024

2023
A 4.0GHz UHS Pseudo Two-port SRAM with BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4nm FinFET Technology.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022
Projection-Based Point Convolution for Efficient Point Cloud Segmentation.
IEEE Access, 2022

2020
PBP-Net: Point Projection and Back-Projection Network for 3D Point Cloud Segmentation.
Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2020

2018
Robust Lane Detection and Tracking for Real-Time Applications.
IEEE Trans. Intell. Transp. Syst., 2018

Regularizing Feature Distribution Using Sliced Wasserstein Distance for Semi-supervised Learning.
Proceedings of the Multi-disciplinary Trends in Artificial Intelligence, 2018

2017
Improving Deep Neural Networks by Adding Auxiliary Information.
Proceedings of the Robot Intelligence Technology and Applications 5, 2017

2016
Design of Light-Weight High-Entropy Alloys.
Entropy, 2016

Design of eMMC controller with multiple channels.
Proceedings of the International SoC Design Conference, 2016

Digital clock data recovery circuit fot S/PDIF.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
An efficient memory control method for video and image processing in digital TV.
Displays, 2015

2014
Arbitration and shuffling algorithm for processing multiple commands in SDRAM controller.
Proceedings of the IEEE International Conference on Consumer Electronics, 2014

2012
Traffic sign detection and identification using SURF algorithm and GPGPU.
Proceedings of the International SoC Design Conference, 2012

2009
A Phase-Based Approach for On-Chip Bus Architecture Optimization.
Comput. J., 2009

2007
A High-Speed Link Layer Architecture for Low Latency and Memory Cost Reduction.
Comput. J., 2007

2006
A High Performance SoC On-chip-bus with Multiple Channels and Routing Processes.
Proceedings of the IFIP VLSI-SoC 2006, 2006

2005
Efficient frequency-domain simulation technique for short-channel MOSFET.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

2004
A new multi-channel on-chip-bus architecture for system-on-chips.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Design of a programmable cryptoprocessor for multiple cryptosystems.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

High performance Viterbi decoder using modified register exchange methods.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004


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